Re: [PATCH v2 10/10] drm/xe/nvm: add support for access mode

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Nov 07, 2024 at 03:13:56PM +0200, Alexander Usyskin wrote:
> Check NVM access mode from GSC FW status registers
> and overwrite access status read from SPI descriptor, if needed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gsc_regs.h |  4 ++++
>  drivers/gpu/drm/xe/xe_heci_gsc.c      |  5 +----
>  drivers/gpu/drm/xe/xe_nvm.c           | 32 ++++++++++++++++++++++++++-
>  3 files changed, 36 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
> index 7702364b65f1..9b66cc972a63 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
> @@ -16,6 +16,10 @@
>  #define MTL_GSC_HECI1_BASE	0x00116000
>  #define MTL_GSC_HECI2_BASE	0x00117000
>  
> +#define DG1_GSC_HECI2_BASE	0x00259000
> +#define PVC_GSC_HECI2_BASE	0x00285000
> +#define DG2_GSC_HECI2_BASE	0x00374000
> +
>  #define HECI_H_CSR(base)	XE_REG((base) + 0x4)
>  #define   HECI_H_CSR_IE		REG_BIT(0)
>  #define   HECI_H_CSR_IS		REG_BIT(1)
> diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c
> index 65b2e147c4b9..27734085164e 100644
> --- a/drivers/gpu/drm/xe/xe_heci_gsc.c
> +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
> @@ -11,14 +11,11 @@
>  #include "xe_device_types.h"
>  #include "xe_drv.h"
>  #include "xe_heci_gsc.h"
> +#include "regs/xe_gsc_regs.h"
>  #include "xe_platform_types.h"
>  
>  #define GSC_BAR_LENGTH  0x00000FFC
>  
> -#define DG1_GSC_HECI2_BASE			0x259000
> -#define PVC_GSC_HECI2_BASE			0x285000
> -#define DG2_GSC_HECI2_BASE			0x374000
> -
>  static void heci_gsc_irq_mask(struct irq_data *d)
>  {
>  	/* generic irq handling */
> diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c
> index 787272761e42..3396bec29c97 100644
> --- a/drivers/gpu/drm/xe/xe_nvm.c
> +++ b/drivers/gpu/drm/xe/xe_nvm.c
> @@ -5,8 +5,11 @@
>  
>  #include <linux/intel_dg_nvm_aux.h>
>  #include <linux/pci.h>
> +#include "xe_device.h"
>  #include "xe_device_types.h"
> +#include "xe_mmio.h"
>  #include "xe_nvm.h"
> +#include "regs/xe_gsc_regs.h"
>  #include "xe_sriov.h"
>  
>  #define GEN12_GUNIT_NVM_BASE 0x00102040
> @@ -24,6 +27,33 @@ static void xe_nvm_release_dev(struct device *dev)
>  {
>  }
>  
> +static bool xe_nvm_writeable_override(struct xe_device *xe)
> +{
> +	struct xe_gt *gt = xe_root_mmio_gt(xe);
> +	resource_size_t base;
> +	bool writeable_override;
> +
> +	if (xe->info.platform == XE_BATTLEMAGE) {
> +		base = DG2_GSC_HECI2_BASE;
> +	} else if (xe->info.platform == XE_PVC) {
> +		base = PVC_GSC_HECI2_BASE;
> +	} else if (xe->info.platform == XE_DG2) {
> +		base = DG2_GSC_HECI2_BASE;
> +	} else if (xe->info.platform == XE_DG1) {
> +		base = DG1_GSC_HECI2_BASE;
> +	} else {
> +		drm_err(&xe->drm, "Unknown platform\n");
> +		return true;
> +	}
> +
> +	writeable_override =
> +		!(xe_mmio_read32(&gt->mmio, HECI_FWSTS2(base)) &
> +		  HECI_FW_STATUS_2_NVM_ACCESS_MODE);
> +	if (writeable_override)
> +		drm_info(&xe->drm, "NVM access overridden by jumper\n");
> +	return writeable_override;
> +}
> +
>  void xe_nvm_init(struct xe_device *xe)
>  {
>  	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> @@ -48,7 +78,7 @@ void xe_nvm_init(struct xe_device *xe)
>  
>  	nvm = xe->nvm;
>  
> -	nvm->writeable_override = false;
> +	nvm->writeable_override = xe_nvm_writeable_override(xe);
>  	nvm->bar.parent = &pdev->resource[0];
>  	nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
>  	nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;
> -- 
> 2.43.0
>