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Thu, 7 Nov 2024 21:40:16 +0000 Date: Thu, 7 Nov 2024 16:40:09 -0500 From: Rodrigo Vivi To: Alexander Usyskin CC: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Oren Weil , , , , , "Tomas Winkler" Subject: Re: [PATCH v2 07/10] drm/i915/nvm: add nvm device for discrete graphics Message-ID: References: <20241107131356.2796969-1-alexander.usyskin@intel.com> <20241107131356.2796969-8-alexander.usyskin@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20241107131356.2796969-8-alexander.usyskin@intel.com> X-ClientProxiedBy: MW4PR03CA0150.namprd03.prod.outlook.com (2603:10b6:303:8c::35) To BYAPR11MB2854.namprd11.prod.outlook.com (2603:10b6:a02:c9::12) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR11MB2854:EE_|SJ0PR11MB4799:EE_ X-MS-Office365-Filtering-Correlation-Id: 24d30aaa-6eec-4c26-33f9-08dcff74c477 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|366016; 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Reviewed-by: Rodrigo Vivi > > CC: Rodrigo Vivi > CC: Lucas De Marchi > Co-developed-by: Tomas Winkler > Signed-off-by: Tomas Winkler > Signed-off-by: Alexander Usyskin > --- > drivers/gpu/drm/i915/Makefile | 4 ++ > drivers/gpu/drm/i915/i915_driver.c | 6 ++ > drivers/gpu/drm/i915/i915_drv.h | 3 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_nvm.c | 94 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_nvm.h | 15 +++++ > 6 files changed, 123 insertions(+) > create mode 100644 drivers/gpu/drm/i915/intel_nvm.c > create mode 100644 drivers/gpu/drm/i915/intel_nvm.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index e033bcaef4f3..09f509843b4e 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -212,6 +212,10 @@ i915-y += \ > i915-y += \ > gt/intel_gsc.o > > +# graphics nvm device (DGFX) support > +i915-y += \ > + intel_nvm.o > + > # graphics hardware monitoring (HWMON) support > i915-$(CONFIG_HWMON) += \ > i915_hwmon.o > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c > index 365329ff8a07..7f7dffdc8852 100644 > --- a/drivers/gpu/drm/i915/i915_driver.c > +++ b/drivers/gpu/drm/i915/i915_driver.c > @@ -80,6 +80,8 @@ > #include "soc/intel_dram.h" > #include "soc/intel_gmch.h" > > +#include "intel_nvm.h" > + > #include "i915_debugfs.h" > #include "i915_driver.h" > #include "i915_drm_client.h" > @@ -620,6 +622,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) > /* Depends on sysfs having been initialized */ > i915_perf_register(dev_priv); > > + intel_nvm_init(dev_priv); > + > for_each_gt(gt, dev_priv, i) > intel_gt_driver_register(gt); > > @@ -663,6 +667,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) > > i915_hwmon_unregister(dev_priv); > > + intel_nvm_fini(dev_priv); > + > i915_perf_unregister(dev_priv); > i915_pmu_unregister(dev_priv); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a66e5bb078cf..faaad8b16ab9 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -67,6 +67,7 @@ > struct drm_i915_clock_gating_funcs; > struct vlv_s0ix_state; > struct intel_pxp; > +struct intel_dg_nvm_dev; > > #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) > > @@ -316,6 +317,8 @@ struct drm_i915_private { > > struct i915_perf perf; > > + struct intel_dg_nvm_dev *nvm; > + > struct i915_hwmon *hwmon; > > struct intel_gt *gt[I915_MAX_GT]; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 818142f5a10c..eddafd5d7628 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -323,6 +323,7 @@ > #define DG2_GSC_HECI2_BASE 0x00374000 > #define MTL_GSC_HECI1_BASE 0x00116000 > #define MTL_GSC_HECI2_BASE 0x00117000 > +#define GEN12_GUNIT_NVM_BASE 0x00102040 > > #define HECI_H_CSR(base) _MMIO((base) + 0x4) > #define HECI_H_CSR_IE REG_BIT(0) > diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_nvm.c > new file mode 100644 > index 000000000000..214c4d47a9cd > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_nvm.c > @@ -0,0 +1,94 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. > + */ > + > +#include > +#include > +#include "i915_reg.h" > +#include "i915_drv.h" > +#include "intel_nvm.h" > + > +#define GEN12_GUNIT_NVM_SIZE 0x80 > + > +static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = { > + [0] = { .name = "DESCRIPTOR", }, > + [2] = { .name = "GSC", }, > + [11] = { .name = "OptionROM", }, > + [12] = { .name = "DAM", }, > +}; > + > +static void i915_nvm_release_dev(struct device *dev) > +{ > +} > + > +void intel_nvm_init(struct drm_i915_private *i915) > +{ > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); > + struct intel_dg_nvm_dev *nvm; > + struct auxiliary_device *aux_dev; > + int ret; > + > + /* Only the DGFX devices have internal NVM */ > + if (!IS_DGFX(i915)) > + return; > + > + /* Nvm pointer should be NULL here */ > + if (WARN_ON(i915->nvm)) > + return; > + > + i915->nvm = kzalloc(sizeof(*nvm), GFP_KERNEL); > + if (!i915->nvm) > + return; > + > + nvm = i915->nvm; > + > + nvm->writeable_override = true; > + nvm->bar.parent = &pdev->resource[0]; > + nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; > + nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; > + nvm->bar.flags = IORESOURCE_MEM; > + nvm->bar.desc = IORES_DESC_NONE; > + nvm->regions = regions; > + > + aux_dev = &nvm->aux_dev; > + > + aux_dev->name = "nvm"; > + aux_dev->id = (pci_domain_nr(pdev->bus) << 16) | > + PCI_DEVID(pdev->bus->number, pdev->devfn); > + aux_dev->dev.parent = &pdev->dev; > + aux_dev->dev.release = i915_nvm_release_dev; > + > + ret = auxiliary_device_init(aux_dev); > + if (ret) { > + drm_err(&i915->drm, "i915-nvm aux init failed %d\n", ret); > + return; > + } > + > + ret = auxiliary_device_add(aux_dev); > + if (ret) { > + drm_err(&i915->drm, "i915-nvm aux add failed %d\n", ret); > + auxiliary_device_uninit(aux_dev); > + return; > + } > +} > + > +void intel_nvm_fini(struct drm_i915_private *i915) > +{ > + struct intel_dg_nvm_dev *nvm = i915->nvm; > + > + /* Only the DGFX devices have internal NVM */ > + if (!IS_DGFX(i915)) > + return; > + > + /* Nvm pointer should not be NULL here */ > + if (WARN_ON(!nvm)) > + return; > + > + drm_err(&i915->drm, "removing i915-nvm cell\n"); > + > + auxiliary_device_delete(&nvm->aux_dev); > + auxiliary_device_uninit(&nvm->aux_dev); > + kfree(nvm); > + i915->nvm = NULL; > +} > diff --git a/drivers/gpu/drm/i915/intel_nvm.h b/drivers/gpu/drm/i915/intel_nvm.h > new file mode 100644 > index 000000000000..7bc3d1114a3f > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_nvm.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright(c) 2019-2024 Intel Corporation. All rights reserved. > + */ > + > +#ifndef __INTEL_NVM_H__ > +#define __INTEL_NVM_H__ > + > +struct drm_i915_private; > + > +void intel_nvm_init(struct drm_i915_private *i915); > + > +void intel_nvm_fini(struct drm_i915_private *i915); > + > +#endif /* __INTEL_NVM_H__ */ > -- > 2.43.0 >