Re: platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Wed, Nov 13, 2024 at 05:33:41PM +0100, Hans de Goede wrote:
> On 13-Nov-24 5:24 PM, Hans de Goede wrote:
> > On 13-Nov-24 4:42 PM, Daniel Walker (danielwa) wrote:

> >> I bisected an issue of a missing pci device to commit 2841631 the commit title
> >> in the subject line which was included in v6.1 stable branch.
> >>
> >> There was a later fix for a similar missing pci device commit 36c676e2 which
> >> appears to be for Goldmont/Apollo Lake. The hardware I'm using is
> >> Goldmont/Denverton. This fix did not appear to change the behavior I'm seeing.
> >>
> >> The pci device which is disappearing is a custom gpio device.
> >>
> >> I tested v6.12-rc5-next to see if any other changes had fixed the issue, but there was
> >> no change in behavior since commit 2841631 .
> >>
> >> When booting up the device is shown in the pci boot messages but the device
> >> doesn't end up making it to lspci once you get to a prompt.
> > 
> > Please give the attached patch a try, this will hopefully fix things.
> > 
> > Once I have confirmation that this fixes things I'll post it to the list.
> > 
> > Note this will not backport to the 6.1 stable branch cleanly due to
> > changes in the x86_cpu_id macros in mainline. Backporting it should
> > be trivial. Please send a backport to stable@vger.kernel.org yourself
> > once this has been merged upstream.
> > 
> > If you backport this, please also backport 36c676e2 first.
> 
> Never mind, self nack. This is correct for Gemini Lake which
> has its SPI at device.function 13.2 like Apollo Lake.
> 
> But looking at the dmesg Denverton actually has it at 1f.1
> aka 31.1 like most other Intel SoCs.
> 
> Which make me wonder why this does not work on Denverton.
> 
> It probably has something to do with these 2 messages:

> pci 0000:00:1f.1: BAR 0 [mem 0xfd000000-0xfdffffff 64bit]: can't claim; no compatible bridge window
> pci 0000:00:1f.1: BAR 0 [mem 0x280000000-0x280ffffff 64bit]: assigned

As I tried to explain in the very first commit that brings the whole driver
into the kernel the P2SB mimics PCI device but actually doesn't provide all
PCI capabilities. The BAR address there is basically a protocol between
firmware and OS which gives the OS the first (most significant) byte of the
address space window of 16Mb that P2SB responds to in HW. So, I haven't
tested if the relocation actually works for this device, esp. if it goes
over 4G boundary.

That said, messing up with that address is most likely a problematic there.

> I'm guessing that this re-assignment is messing up
> the p2sb BAR caching, after which things go wrong.
> 
> Daniel, are you seeing similar messages with a working kernel ?

-- 
With Best Regards,
Andy Shevchenko