From: "Liang, Kan" <kan.liang@linux.intel.com>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: mingo@redhat.com, acme@kernel.org, namhyung@kernel.org,
tglx@linutronix.de, dave.hansen@linux.intel.com,
irogers@google.com, adrian.hunter@intel.com, jolsa@kernel.org,
alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org,
ak@linux.intel.com, zide.chen@intel.com
Subject: Re: [RFC PATCH 00/12] Support vector and more extended registers in perf
Date: Wed, 18 Jun 2025 06:47:20 -0400 [thread overview]
Message-ID: <a116761e-30bc-49bf-a1f8-9cc0ec1faae2@linux.intel.com> (raw)
In-Reply-To: <1121293d-777e-4c21-b1ad-d34516d2cd3a@linux.intel.com>
On 2025-06-17 8:57 p.m., Mi, Dapeng wrote:
>
> On 6/17/2025 11:23 PM, Liang, Kan wrote:
>>
>> On 2025-06-17 10:29 a.m., Peter Zijlstra wrote:
>>> On Tue, Jun 17, 2025 at 09:52:12AM -0400, Liang, Kan wrote:
>>>
>>>> OK. So the sample_simd_reg_words actually has another meaning now.
>>> Well, any simd field being non-zero means userspace knows about it. Sort
>>> of an implicit flag.
>> Yes, but the tool probably wouldn't to touch any simd fields if user
>> doesn't ask for simd registers
>>
>>>> It's used as a flag to tell whether utilizing the old format.
>>>>
>>>> If so, I think it may be better to have a dedicate sample_simd_reg_flag
>>>> field.
>>>>
>>>> For example,
>>>>
>>>> #define SAMPLE_SIMD_FLAGS_FORMAT_LEGACY 0x0
>>>> #define SAMPLE_SIMD_FLAGS_FORMAT_WORDS 0x1
>>>>
>>>> __u8 sample_simd_reg_flags;
>>>> __u8 sample_simd_reg_words;
>>>> __u64 sample_simd_reg_intr;
>>>> __u64 sample_simd_reg_user;
>>>>
>>>> If (sample_simd_reg_flags != 0) reclaims the XMM space for APX and SPP.
>>>>
>>>> Does it make sense?
>
> Not sure if I missed some discussion, but are these fields only intended
> for SIMD regs? What about the APX extended GPRs? Suppose APX eGPRs can
> reuse the legacy XMM bitmaps in sample_regs_user/intr[47:32], but we need
> an extra flag to distinguish it's XMM regs or APX eGPRs, maybe add an extra
> bit sample_egpr_reg : 1 in sample_simd_reg_words, but the *simd* word in
> the name would become ambiguous.
It can be used to explicitly tell the kernel that a new format is
expected. The new format means
- Put APX and SPP into sample_regs_user/intr[47:32]
- Use the sample_simd_reg_*
Alternatively, as Peter suggested, we can use the sample_simd_reg_words
to imply the new format.
If so, I will make it an union, for example.
union {
__u16 sample_reg_flags;
__u16 sample_simd_reg_words;
};
The first thing the tool does should be to set sample_reg_flags = 1,
regardless of whether simd is requested.
>
>
>>> Not sure, it eats up a whole byte. Dapeng seemed to favour separate
>>> intr/user vector width (although I'm not quite sure what the use would
>>> be).
>
> The reason that I prefer to add 2 separate "words" item is that user could
> sample interrupt and user space SIMD regs (but with different bit-width)
> simultaneously in theory, like "--intr-regs=YMM0, --user-regs=XMM0".
I'm not sure why the user wants a different bit-width. The
--user-regs=XMM0" doesn't seem to provide more useful information.
Anyway, I believe the tool can handle this case. The tool can always ask
YMM0 for both --intr-regs and --user-regs, but only output the XMM0 for
--user-regs. The only drawback is that the kernel may dump extra
information for the --user-regs. I don't think it's a big problem.
Thanks,
Kan
>
>
>>>
>>> If you want an explicit bit, we might as well use one from __reserved_1,
>>> we still have some left.
>> OK. I may add a sample_simd_reg : 1 to explicitly tell kernel to utilize
>> the sample_simd_reg_XXX.
>>
>> Thanks,
>> Kan
next prev parent reply other threads:[~2025-06-18 10:48 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 13:49 [RFC PATCH 00/12] Support vector and more extended registers in perf kan.liang
2025-06-13 13:49 ` [RFC PATCH 01/12] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-13 13:49 ` [RFC PATCH 02/12] perf/x86: Setup the regs data kan.liang
2025-06-13 13:49 ` [RFC PATCH 03/12] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-06-13 14:39 ` Dave Hansen
2025-06-13 14:54 ` Liang, Kan
2025-06-13 15:19 ` Dave Hansen
2025-06-13 13:49 ` [RFC PATCH 04/12] perf: Move has_extended_regs() to header file kan.liang
2025-06-13 13:49 ` [RFC PATCH 05/12] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-13 15:15 ` Dave Hansen
2025-06-13 17:51 ` Liang, Kan
2025-06-13 15:34 ` Dave Hansen
2025-06-13 18:14 ` Liang, Kan
2025-06-13 13:49 ` [RFC PATCH 06/12] perf: Support extension of sample_regs kan.liang
2025-06-17 8:00 ` Mi, Dapeng
2025-06-17 8:14 ` Peter Zijlstra
2025-06-17 9:49 ` Mi, Dapeng
2025-06-17 10:28 ` Peter Zijlstra
2025-06-17 12:14 ` Mi, Dapeng
2025-06-17 13:33 ` Peter Zijlstra
2025-06-17 14:06 ` Peter Zijlstra
2025-06-17 14:24 ` Mark Rutland
2025-06-17 14:44 ` Peter Zijlstra
2025-06-17 14:55 ` Mark Rutland
2025-06-17 19:00 ` Mark Brown
2025-06-17 20:32 ` Liang, Kan
2025-06-18 9:35 ` Peter Zijlstra
2025-06-18 10:10 ` Liang, Kan
2025-06-18 13:30 ` Peter Zijlstra
2025-06-18 13:52 ` Liang, Kan
2025-06-18 14:30 ` Dave Hansen
2025-06-18 14:47 ` Dave Hansen
2025-06-18 15:24 ` Liang, Kan
2025-06-18 14:45 ` Peter Zijlstra
2025-06-18 15:22 ` Liang, Kan
2025-06-13 13:49 ` [RFC PATCH 07/12] perf/x86: Add YMMH in extended regs kan.liang
2025-06-13 15:48 ` Dave Hansen
2025-06-13 13:49 ` [RFC PATCH 08/12] perf/x86: Add APX " kan.liang
2025-06-13 16:02 ` Dave Hansen
2025-06-13 17:17 ` Liang, Kan
2025-06-17 8:19 ` Peter Zijlstra
2025-06-13 13:49 ` [RFC PATCH 09/12] perf/x86: Add OPMASK " kan.liang
2025-06-13 13:49 ` [RFC PATCH 10/12] perf/x86: Add ZMM " kan.liang
2025-06-13 13:49 ` [RFC PATCH 11/12] perf/x86: Add SSP " kan.liang
2025-06-13 13:49 ` [RFC PATCH 12/12] perf/x86/intel: Support extended registers kan.liang
2025-06-17 7:50 ` [RFC PATCH 00/12] Support vector and more extended registers in perf Mi, Dapeng
2025-06-17 8:24 ` Peter Zijlstra
2025-06-17 13:52 ` Liang, Kan
2025-06-17 14:29 ` Peter Zijlstra
2025-06-17 15:23 ` Liang, Kan
2025-06-17 17:34 ` Peter Zijlstra
2025-06-18 0:57 ` Mi, Dapeng
2025-06-18 10:47 ` Liang, Kan [this message]
2025-06-18 12:28 ` Mi, Dapeng
2025-06-18 13:15 ` Liang, Kan
2025-06-19 0:41 ` Mi, Dapeng
2025-06-19 11:11 ` Liang, Kan
2025-06-19 12:26 ` Mi, Dapeng
2025-06-19 13:38 ` Peter Zijlstra
2025-06-19 14:27 ` Liang, Kan
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