From: Tim Chen <tim.c.chen@linux.intel.com>
To: Jiri Kosina <jikos@kernel.org>, Thomas Gleixner <tglx@linutronix.de>
Cc: Tim Chen <tim.c.chen@linux.intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Ingo Molnar <mingo@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Andrea Arcangeli <aarcange@redhat.com>,
David Woodhouse <dwmw@amazon.co.uk>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Casey Schaufler <casey.schaufler@intel.com>,
Asit Mallick <asit.k.mallick@intel.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Jon Masters <jcm@redhat.com>, Waiman Long <longman9394@gmail.com>,
linux-kernel@vger.kernel.org, x86@kernel.org
Subject: [Patch v4 17/18] x86/speculation: Update SPEC_CTRL MSRs of remote CPUs
Date: Tue, 30 Oct 2018 11:49:24 -0700 [thread overview]
Message-ID: <a14236d8b56dafe6988ce1b266a6e929be5296a8.1540923609.git.tim.c.chen@linux.intel.com> (raw)
In-Reply-To: <cover.1540923609.git.tim.c.chen@linux.intel.com>
In-Reply-To: <cover.1540923609.git.tim.c.chen@linux.intel.com>
The SPEC_CTRL MSR of a remote CPU cannot be updated immediately when
TIF_STIBP flag is changed on a task running on the remote CPU.
If next task's TIF_STIBP flag happened to be the same as the updated
TIF_STIBP on the previous task on the next context switch, the SPEC_CTRL
MSR update is missed as the SPEC_CTRL MSR update occurs only on flag
changes, and update of the SPEC_CTRL MSR did not happen while previous
task was running.
This patch creates TIF_UPDATE_SPEC_CTRL bit and set it along with
TIF_STIBP bit update for tasks running on remote CPU. This signals that
the SPEC_CTRL MSR has a pending forced update on the next context
switch.
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
---
arch/x86/include/asm/thread_info.h | 6 +++++-
arch/x86/kernel/cpu/bugs.c | 2 ++
arch/x86/kernel/process.c | 22 +++++++++++++++++++++-
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 4f6a7a9..7bdd097 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -97,6 +97,7 @@ struct thread_info {
#define TIF_USER_RETURN_NOTIFY 14 /* Notify kernel of userspace return */
#define TIF_PATCH_PENDING 15 /* Pending live patching update */
#define TIF_FSCHECK 16 /* Check FS is USER_DS on return */
+#define TIF_UPDATE_SPEC_CTRL 17 /* Pending update of speculation control MSR */
/* Task status */
#define TIF_UPROBE 18 /* Breakpointed or singlestepping */
@@ -131,6 +132,7 @@ struct thread_info {
#define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY)
#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING)
#define _TIF_FSCHECK (1 << TIF_FSCHECK)
+#define _TIF_UPDATE_SPEC_CTRL (1 << TIF_UPDATE_SPEC_CTRL)
#define _TIF_UPROBE (1 << TIF_UPROBE)
#define _TIF_MEMDIE (1 << TIF_MEMDIE)
@@ -166,7 +168,9 @@ struct thread_info {
(_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP| \
_TIF_SSBD|_TIF_STIBP)
-#define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
+#define _TIF_WORK_CTXSW_PREV \
+ (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY|_TIF_UPDATE_SPEC_CTRL)
+
#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
#define STACK_WARN (THREAD_SIZE/8)
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index b402b96..1ba9cb5 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -789,6 +789,8 @@ static void set_task_stibp(struct task_struct *tsk, bool stibp_on)
if (tsk == current)
speculation_ctrl_update_current();
+ else if (task_cpu(tsk) != smp_processor_id())
+ set_tsk_thread_flag(tsk, TIF_UPDATE_SPEC_CTRL);
}
void arch_set_security(struct task_struct *tsk, unsigned int value)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 943e90d..048b7f4b 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -426,7 +426,19 @@ static __always_inline void spec_ctrl_update_msr(unsigned long tifn)
static __always_inline void __speculation_ctrl_update(unsigned long tifp,
unsigned long tifn)
{
- bool updmsr = !!((tifp ^ tifn) & _TIF_STIBP);
+ /*
+ * If TIF_UPDATE_SPEC_CTRL bit is set in tifp, speculation related
+ * TIF flags have changed when previous task was running, but
+ * SPEC_CTRL MSR has not been synchronized with TIF flag changes.
+ * SPEC_CTRL MSR value can be out of date.
+ *
+ * Need to force update SPEC_CTRL MSR if TIF_UPDATE_SPEC_CTRL
+ * bit in tifp is set.
+ *
+ * The TIF_UPDATE_SPEC_CTRL bit in tifn was cleared before calling
+ * this function.
+ */
+ bool updmsr = !!((tifp ^ tifn) & (_TIF_STIBP|_TIF_UPDATE_SPEC_CTRL));
/* If TIF_SSBD is different, select the proper mitigation method */
if ((tifp ^ tifn) & _TIF_SSBD) {
@@ -482,6 +494,14 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
if ((tifp ^ tifn) & _TIF_NOCPUID)
set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
+ if (tifp & _TIF_UPDATE_SPEC_CTRL)
+ clear_tsk_thread_flag(prev_p, TIF_UPDATE_SPEC_CTRL);
+
+ if (tifn & _TIF_UPDATE_SPEC_CTRL) {
+ clear_tsk_thread_flag(next_p, TIF_UPDATE_SPEC_CTRL);
+ tifn &= ~_TIF_UPDATE_SPEC_CTRL;
+ }
+
__speculation_ctrl_update(tifp, tifn);
}
--
2.9.4
next prev parent reply other threads:[~2018-10-30 19:22 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-30 18:49 [Patch v4 00/18] Provide process property based options to enable Spectre v2 userspace-userspace protection* Tim Chen
2018-10-30 18:49 ` [Patch v4 01/18] x86/speculation: Clean up spectre_v2_parse_cmdline() Tim Chen
2018-10-30 18:49 ` [Patch v4 02/18] x86/speculation: Remove unnecessary ret variable in cpu_show_common() Tim Chen
2018-10-30 18:49 ` [Patch v4 03/18] x86/speculation: Reorganize cpu_show_common() Tim Chen
2018-11-03 18:07 ` Thomas Gleixner
2018-11-05 19:12 ` Tim Chen
2018-11-05 19:17 ` Thomas Gleixner
2018-10-30 18:49 ` [Patch v4 04/18] x86/speculation: Add X86_FEATURE_USE_IBRS_ENHANCED Tim Chen
2018-10-30 18:49 ` [Patch v4 05/18] x86/speculation: Disable STIBP when enhanced IBRS is in use Tim Chen
2018-10-30 18:49 ` [Patch v4 06/18] smt: Create cpu_smt_enabled static key for SMT specific code Tim Chen
2018-10-30 18:49 ` [Patch v4 07/18] x86/smt: Convert cpu_smt_control check to cpu_smt_enabled static key Tim Chen
2018-11-03 18:29 ` Thomas Gleixner
2018-11-08 1:43 ` Tim Chen
2018-11-08 11:18 ` Thomas Gleixner
2018-10-30 18:49 ` [Patch v4 08/18] sched: Deprecate sched_smt_present and use " Tim Chen
2018-11-03 18:20 ` Thomas Gleixner
2018-11-09 22:08 ` Tim Chen
2018-10-30 18:49 ` [Patch v4 09/18] x86/speculation: Rename SSBD update functions Tim Chen
2018-10-30 18:49 ` [Patch v4 10/18] x86/speculation: Reorganize speculation control MSRs update Tim Chen
2018-10-30 18:49 ` [Patch v4 11/18] x86/speculation: Update comment on TIF_SSBD Tim Chen
2018-10-30 18:49 ` [Patch v4 12/18] x86: Group thread info flags by functionality Tim Chen
2018-10-30 18:49 ` [Patch v4 13/18] security: Update security level of a process when modifying its dumpability Tim Chen
2018-10-30 20:57 ` Schaufler, Casey
2018-10-30 21:30 ` Tim Chen
2018-10-30 21:53 ` Schaufler, Casey
2018-10-30 18:49 ` [Patch v4 14/18] x86/speculation: Turn on or off STIBP according to a task's TIF_STIBP Tim Chen
2018-10-30 18:49 ` [Patch v4 15/18] x86/speculation: Add Spectre v2 app to app protection modes Tim Chen
2018-10-30 18:49 ` [Patch v4 16/18] x86/speculation: Enable STIBP to protect security sensitive tasks Tim Chen
2018-10-30 21:07 ` Schaufler, Casey
2018-10-30 21:34 ` Tim Chen
2018-10-30 22:02 ` Schaufler, Casey
2018-10-30 18:49 ` Tim Chen [this message]
2018-11-04 19:49 ` [Patch v4 17/18] x86/speculation: Update SPEC_CTRL MSRs of remote CPUs Thomas Gleixner
2018-11-05 22:02 ` Tim Chen
2018-11-05 23:04 ` Thomas Gleixner
2018-11-05 23:59 ` Tim Chen
2018-11-06 7:46 ` Thomas Gleixner
2018-11-07 0:18 ` Tim Chen
2018-11-07 18:33 ` Waiman Long
2018-11-07 23:15 ` Tim Chen
2018-11-07 23:03 ` Thomas Gleixner
2018-11-08 0:22 ` Tim Chen
2018-10-30 18:49 ` [Patch v4 18/18] x86/speculation: Create PRCTL interface to restrict indirect branch speculation Tim Chen
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