From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Andrei Vagin <avagin@gmail.com>
Cc: Andrei Vagin <avagin@google.com>,
Thomas Gleixner <tglx@kernel.org>,
"Ingo Molnar" <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
<linux-kernel@vger.kernel.org>, <criu@lists.linux.dev>,
<x86@kernel.org>, <stable@vger.kernel.org>
Subject: Re: [PATCH] Revert "x86/fpu: Refine and simplify the magic number check during signal return"
Date: Wed, 29 Apr 2026 14:44:25 -0700 [thread overview]
Message-ID: <a1614b76-192f-41b3-a4e9-a4ce6816d745@intel.com> (raw)
In-Reply-To: <CANaxB-y4wh3JYUctDMWVuuOz9ZhVH9RAwopPZQ39JfmxkjN56g@mail.gmail.com>
On 4/29/2026 1:44 PM, Andrei Vagin wrote:
>
> Enforcing validation against 'fpstate->user_size' instead of the frame's
> own 'fx_sw->xstate_size' changes the kernel ABI, it isn't strengthen the
> sanity check logic. When user-space supplies a valid, self-consistent
> frame with an explicit size that older kernels accepted, and the updated
> logic rejects it, which triggers a userspace regression.
Sorry, I don't get your version of ABI.
Eventually, XRSTOR will execute to restore the state. The kernel tracks
each task's requested feature bitmap (RFBM), which determines the size.
As describe SDM Vol.1, Section 13.13:
An execution of an instruction in the XSAVE feature set may access
any byte of any state component on which that execution operates even
when saving a state component is omitted ...
Given this, the kernel must ensure the backing memory is valid and
sufficient. So this consistency does matter.
Thanks,
Chang
next prev parent reply other threads:[~2026-04-29 21:44 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-29 0:06 [PATCH] Revert "x86/fpu: Refine and simplify the magic number check during signal return" Andrei Vagin
2026-04-29 7:26 ` Chang S. Bae
2026-04-29 16:44 ` Andrei Vagin
2026-04-29 17:15 ` Chang S. Bae
2026-04-29 20:44 ` Andrei Vagin
2026-04-29 21:44 ` Chang S. Bae [this message]
2026-04-30 0:28 ` Andrei Vagin
2026-05-01 18:44 ` Andrei Vagin
2026-05-01 19:13 ` Chang S. Bae
2026-05-01 20:50 ` Andrei Vagin
2026-05-01 21:04 ` Chang S. Bae
2026-05-01 21:42 ` Andrei Vagin
2026-05-02 19:23 ` Chang S. Bae
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