From: Jon Hunter <jonathanh@nvidia.com>
To: Sagar Kamble <skamble@nvidia.com>,
thierry.reding@gmail.com, digetx@gmail.com,
yangyingliang@huawei.com, ndesaulniers@google.com,
pshete@nvidia.com, nathan@kernel.org, kkartik@nvidia.com,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] soc/tegra: fuse: Add nvmem cell lookup entries for tegra194
Date: Tue, 5 Apr 2022 13:44:07 +0100 [thread overview]
Message-ID: <a31d9fe6-3052-d09d-c012-3e141a4ffde3@nvidia.com> (raw)
In-Reply-To: <1648123728-16737-1-git-send-email-skamble@nvidia.com>
On 24/03/2022 12:08, Sagar Kamble wrote:
> Add nvmem cell lookup entries for below fuse cells:
> - gcplex-config-fuse
> - pdi0
> - pdi1
>
> Also include the device name prefix "gpu-" in the names of the gpu fuse
> cells in nvmem_cell_info.
>
> Signed-off-by: Sagar Kamble <skamble@nvidia.com>
> ---
> drivers/soc/tegra/fuse/fuse-tegra.c | 8 ++++----
> drivers/soc/tegra/fuse/fuse-tegra30.c | 17 ++++++++++++++++-
> 2 files changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
> index aa94fda282f4..b0a8405dbdb1 100644
> --- a/drivers/soc/tegra/fuse/fuse-tegra.c
> +++ b/drivers/soc/tegra/fuse/fuse-tegra.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
> */
>
> #include <linux/clk.h>
> @@ -162,7 +162,7 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
> .bit_offset = 0,
> .nbits = 32,
> }, {
> - .name = "gcplex-config-fuse",
> + .name = "gpu-gcplex-config-fuse",
> .offset = 0x1c8,
> .bytes = 4,
> .bit_offset = 0,
> @@ -186,13 +186,13 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
> .bit_offset = 0,
> .nbits = 32,
> }, {
> - .name = "pdi0",
> + .name = "gpu-pdi0",
> .offset = 0x300,
> .bytes = 4,
> .bit_offset = 0,
> .nbits = 32,
> }, {
> - .name = "pdi1",
> + .name = "gpu-pdi1",
> .offset = 0x304,
> .bytes = 4,
> .bit_offset = 0,
> diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
> index b071d433d74f..f01d8a2547b6 100644
> --- a/drivers/soc/tegra/fuse/fuse-tegra30.c
> +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
> */
>
> #include <linux/device.h>
> @@ -344,6 +344,21 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
> .cell_name = "xusb-pad-calibration-ext",
> .dev_id = "3520000.padctl",
> .con_id = "calibration-ext",
> + }, {
> + .nvmem_name = "fuse",
> + .cell_name = "gpu-gcplex-config-fuse",
> + .dev_id = "17000000.gpu",
> + .con_id = "gcplex-config-fuse",
> + }, {
> + .nvmem_name = "fuse",
> + .cell_name = "gpu-pdi0",
> + .dev_id = "17000000.gpu",
> + .con_id = "pdi0",
> + }, {
> + .nvmem_name = "fuse",
> + .cell_name = "gpu-pdi1",
> + .dev_id = "17000000.gpu",
> + .con_id = "pdi1",
> },
> };
>
Thanks! Looks good to me.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Jon
--
nvpublic
next prev parent reply other threads:[~2022-04-06 0:17 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 12:08 [PATCH 1/1] soc/tegra: fuse: Add nvmem cell lookup entries for tegra194 Sagar Kamble
2022-04-05 12:44 ` Jon Hunter [this message]
2022-04-06 12:59 ` Thierry Reding
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