* [PATCH v2] arm64: dts: s32g: add I2C support
@ 2024-12-13 14:22 Ciprian Costea
2024-12-13 19:15 ` Frank Li
0 siblings, 1 reply; 3+ messages in thread
From: Ciprian Costea @ 2024-12-13 14:22 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Add the I2C Devicetree nodes and pinmux for S32G2 and S32G3 SoCs.
With respect to S32G2/S32G3 SoC based boards, there are multiple RDB
(rdb2 vs rdb3) and EVB (for G2 vs for G3) board revisions. These versions
are quite similar. The common part for the EVB revisions will be
centralized in 's32gxxa-evb.dtsi' file, while the RDB commonalities will
be placed in 's32gxxa-rdb.dtsi' file.
This refactor will also serve for other modules in the future, such as
FlexCAN, DSPI.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 45 ++++++
.../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
.../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
arch/arm64/boot/dts/freescale/s32g3.dtsi | 50 ++++++
.../boot/dts/freescale/s32g399a-rdb3.dts | 9 ++
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
.../boot/dts/freescale/s32gxxxa-rdb.dtsi | 126 +++++++++++++++
7 files changed, 382 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 7be430b78c83..0e6c847ab0c3 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -333,6 +333,33 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ i2c0: i2c@401e4000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x401e4000 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c1: i2c@401e8000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x401e8000 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c2: i2c@401ec000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x401ec000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
uart2: serial@402bc000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
@@ -341,6 +368,24 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ i2c3: i2c@402d8000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x402d8000 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c4: i2c@402dc000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x402dc000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index b9a119eea2b7..c4a195dd67bf 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "s32g2.dtsi"
+#include "s32gxxxa-evb.dtsi"
/ {
model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index aaa61a8ad0da..b5ba51696f43 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "s32g2.dtsi"
+#include "s32gxxxa-rdb.dtsi"
/ {
model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 6c572ffe37ca..666e4029e588 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -390,6 +390,36 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ i2c0: i2c@401e4000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401e4000 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c1: i2c@401e8000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401e8000 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c2: i2c@401ec000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401ec000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
uart2: serial@402bc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
@@ -398,6 +428,26 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ i2c3: i2c@402d8000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x402d8000 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c4: i2c@402dc000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x402dc000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
index 828e353455b5..5f8739c068c6 100644
--- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
+++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "s32g3.dtsi"
+#include "s32gxxxa-rdb.dtsi"
/ {
model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
@@ -39,6 +40,14 @@ &uart1 {
status = "okay";
};
+&i2c4 {
+ ina231@40 {
+ compatible = "ti,ina231";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+};
+
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
new file mode 100644
index 000000000000..a44eff28073a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2024 NXP
+ *
+ * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
+ * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
+ * Larisa Grigore <larisa.grigore@nxp.com>
+ */
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ i2c0-grp0 {
+ pinmux = <0x101>, <0x111>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-grp1 {
+ pinmux = <0x2352>, <0x2362>;
+ };
+ };
+
+ i2c0_gpio_pins: i2c0-gpio-pins {
+ i2c0-gpio-grp0 {
+ pinmux = <0x100>, <0x110>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-gpio-grp1 {
+ pinmux = <0x2350>, <0x2360>;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ i2c1-grp0 {
+ pinmux = <0x131>, <0x141>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c1-grp1 {
+ pinmux = <0x2cd2>, <0x2ce2>;
+ };
+ };
+
+ i2c1_gpio_pins: i2c1-gpio-pins {
+ i2c1-gpio-grp0 {
+ pinmux = <0x130>, <0x140>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c1-gpio-grp1 {
+ pinmux = <0x2cd0>, <0x2ce0>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-grp0 {
+ pinmux = <0x151>, <0x161>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-grp1 {
+ pinmux = <0x2cf2>, <0x2d02>;
+ };
+ };
+
+ i2c2_gpio_pins: i2c2-gpio-pins {
+ i2c2-gpio-grp0 {
+ pinmux = <0x150>, <0x160>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-gpio-grp1 {
+ pinmux = <0x2cf0>, <0x2d00>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ i2c4-grp0 {
+ pinmux = <0x211>, <0x222>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-grp1 {
+ pinmux = <0x2d43>, <0x2d33>;
+ };
+ };
+
+ i2c4_gpio_pins: i2c4-gpio-pins {
+ i2c4-gpio-grp0 {
+ pinmux = <0x210>, <0x220>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-gpio-grp1 {
+ pinmux = <0x2d40>, <0x2d30>;
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&i2c0_gpio_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&i2c1_gpio_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&i2c4_gpio_pins>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
new file mode 100644
index 000000000000..50fe6aaa1605
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2024 NXP
+ *
+ * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
+ * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
+ * Larisa Grigore <larisa.grigore@nxp.com>
+ */
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ i2c0-grp0 {
+ pinmux = <0x1f2>, <0x201>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-grp1 {
+ pinmux = <0x2353>, <0x2363>;
+ };
+ };
+
+ i2c0_gpio_pins: i2c0-gpio-pins {
+ i2c0-gpio-grp0 {
+ pinmux = <0x1f0>, <0x200>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-gpio-grp1 {
+ pinmux = <0x2350>, <0x2360>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-grp0 {
+ pinmux = <0x151>, <0x161>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-grp1 {
+ pinmux = <0x2cf2>, <0x2d02>;
+ };
+ };
+
+ i2c2_gpio_pins: i2c2-gpio-pins {
+ i2c2-gpio-grp0 {
+ pinmux = <0x2cf0>, <0x2d00>;
+ };
+
+ i2c2-gpio-grp1 {
+ pinmux = <0x150>, <0x160>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ i2c4-grp0 {
+ pinmux = <0x211>, <0x222>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-grp1 {
+ pinmux = <0x2d43>, <0x2d33>;
+ };
+ };
+
+ i2c4_gpio_pins: i2c4-gpio-pins {
+ i2c4-gpio-grp0 {
+ pinmux = <0x210>, <0x220>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-gpio-grp1 {
+ pinmux = <0x2d40>, <0x2d30>;
+ };
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&i2c0_gpio_pins>;
+ status = "okay";
+
+ pcal6524: gpio-expander@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ status = "okay";
+};
+
+&i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&i2c4_gpio_pins>;
+ status = "okay";
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: s32g: add I2C support
2024-12-13 14:22 [PATCH v2] arm64: dts: s32g: add I2C support Ciprian Costea
@ 2024-12-13 19:15 ` Frank Li
2024-12-19 8:11 ` Ciprian Marian Costea
0 siblings, 1 reply; 3+ messages in thread
From: Frank Li @ 2024-12-13 19:15 UTC (permalink / raw)
To: Ciprian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On Fri, Dec 13, 2024 at 04:22:50PM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add the I2C Devicetree nodes and pinmux for S32G2 and S32G3 SoCs.
>
> With respect to S32G2/S32G3 SoC based boards, there are multiple RDB
> (rdb2 vs rdb3) and EVB (for G2 vs for G3) board revisions. These versions
> are quite similar. The common part for the EVB revisions will be
> centralized in 's32gxxa-evb.dtsi' file, while the RDB commonalities will
> be placed in 's32gxxa-rdb.dtsi' file.
>
> This refactor will also serve for other modules in the future, such as
> FlexCAN, DSPI.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
Change log here!
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 45 ++++++
> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
Shawn require board dts should be seperate patch
> .../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 50 ++++++
> .../boot/dts/freescale/s32g399a-rdb3.dts | 9 ++
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 126 +++++++++++++++
> 7 files changed, 382 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..0e6c847ab0c3 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -333,6 +333,33 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -341,6 +368,24 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g2-usdhc";
> reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> index b9a119eea2b7..c4a195dd67bf 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-evb.dtsi"
>
> / {
> model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> index aaa61a8ad0da..b5ba51696f43 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..666e4029e588 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -390,6 +390,36 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -398,6 +428,26 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g3-usdhc",
> "nxp,s32g2-usdhc";
> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> index 828e353455b5..5f8739c068c6 100644
> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "s32g3.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
> @@ -39,6 +40,14 @@ &uart1 {
> status = "okay";
> };
>
> +&i2c4 {
> + ina231@40 {
> + compatible = "ti,ina231";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> +};
> +
> &usdhc0 {
> pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-0 = <&pinctrl_usdhc0>;
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> new file mode 100644
> index 000000000000..a44eff28073a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x101>, <0x111>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2352>, <0x2362>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x100>, <0x110>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + i2c1-grp0 {
> + pinmux = <0x131>, <0x141>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-grp1 {
> + pinmux = <0x2cd2>, <0x2ce2>;
> + };
> + };
> +
> + i2c1_gpio_pins: i2c1-gpio-pins {
> + i2c1-gpio-grp0 {
> + pinmux = <0x130>, <0x140>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-gpio-grp1 {
> + pinmux = <0x2cd0>, <0x2ce0>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&i2c1_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> new file mode 100644
> index 000000000000..50fe6aaa1605
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -0,0 +1,126 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x1f2>, <0x201>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2353>, <0x2363>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x1f0>, <0x200>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
I remember I have said "#address-cells" and "#size-cells" should be in
dtsi to avoid copy it at each board dts file.
Frank
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +
> + pcal6524: gpio-expander@22 {
> + compatible = "nxp,pcal6524";
> + reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: s32g: add I2C support
2024-12-13 19:15 ` Frank Li
@ 2024-12-19 8:11 ` Ciprian Marian Costea
0 siblings, 0 replies; 3+ messages in thread
From: Ciprian Marian Costea @ 2024-12-19 8:11 UTC (permalink / raw)
To: Frank Li
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On 12/13/2024 9:15 PM, Frank Li wrote:
> On Fri, Dec 13, 2024 at 04:22:50PM +0200, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add the I2C Devicetree nodes and pinmux for S32G2 and S32G3 SoCs.
>>
>> With respect to S32G2/S32G3 SoC based boards, there are multiple RDB
>> (rdb2 vs rdb3) and EVB (for G2 vs for G3) board revisions. These versions
>> are quite similar. The common part for the EVB revisions will be
>> centralized in 's32gxxa-evb.dtsi' file, while the RDB commonalities will
>> be placed in 's32gxxa-rdb.dtsi' file.
>>
>> This refactor will also serve for other modules in the future, such as
>> FlexCAN, DSPI.
>>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>
> Change log here!
Hello Frank,
Yes, I forgot to add it. I will add the changelog in V3.
>
>> arch/arm64/boot/dts/freescale/s32g2.dtsi | 45 ++++++
>> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
>
> Shawn require board dts should be seperate patch
>
Sure. I can break the commit into two parts (common & board dts I2C
support) in V3.
>> .../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
>> arch/arm64/boot/dts/freescale/s32g3.dtsi | 50 ++++++
>> .../boot/dts/freescale/s32g399a-rdb3.dts | 9 ++
>> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
>> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 126 +++++++++++++++
>> 7 files changed, 382 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
>> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> index 7be430b78c83..0e6c847ab0c3 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> @@ -333,6 +333,33 @@ uart1: serial@401cc000 {
>> status = "disabled";
>> };
>>
>> + i2c0: i2c@401e4000 {
>> + compatible = "nxp,s32g2-i2c";
>> + reg = <0x401e4000 0x1000>;
>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> + i2c1: i2c@401e8000 {
>> + compatible = "nxp,s32g2-i2c";
>> + reg = <0x401e8000 0x1000>;
>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> + i2c2: i2c@401ec000 {
>> + compatible = "nxp,s32g2-i2c";
>> + reg = <0x401ec000 0x1000>;
>> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> uart2: serial@402bc000 {
>> compatible = "nxp,s32g2-linflexuart",
>> "fsl,s32v234-linflexuart";
>> @@ -341,6 +368,24 @@ uart2: serial@402bc000 {
>> status = "disabled";
>> };
>>
>> + i2c3: i2c@402d8000 {
>> + compatible = "nxp,s32g2-i2c";
>> + reg = <0x402d8000 0x1000>;
>> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> + i2c4: i2c@402dc000 {
>> + compatible = "nxp,s32g2-i2c";
>> + reg = <0x402dc000 0x1000>;
>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> usdhc0: mmc@402f0000 {
>> compatible = "nxp,s32g2-usdhc";
>> reg = <0x402f0000 0x1000>;
>> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
>> index b9a119eea2b7..c4a195dd67bf 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
>> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
>> @@ -7,6 +7,7 @@
>> /dts-v1/;
>>
>> #include "s32g2.dtsi"
>> +#include "s32gxxxa-evb.dtsi"
>>
>> / {
>> model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
>> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>> index aaa61a8ad0da..b5ba51696f43 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>> @@ -7,6 +7,7 @@
>> /dts-v1/;
>>
>> #include "s32g2.dtsi"
>> +#include "s32gxxxa-rdb.dtsi"
>>
>> / {
>> model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
>> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> index 6c572ffe37ca..666e4029e588 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> @@ -390,6 +390,36 @@ uart1: serial@401cc000 {
>> status = "disabled";
>> };
>>
>> + i2c0: i2c@401e4000 {
>> + compatible = "nxp,s32g3-i2c",
>> + "nxp,s32g2-i2c";
>> + reg = <0x401e4000 0x1000>;
>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> + i2c1: i2c@401e8000 {
>> + compatible = "nxp,s32g3-i2c",
>> + "nxp,s32g2-i2c";
>> + reg = <0x401e8000 0x1000>;
>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> + i2c2: i2c@401ec000 {
>> + compatible = "nxp,s32g3-i2c",
>> + "nxp,s32g2-i2c";
>> + reg = <0x401ec000 0x1000>;
>> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> uart2: serial@402bc000 {
>> compatible = "nxp,s32g3-linflexuart",
>> "fsl,s32v234-linflexuart";
>> @@ -398,6 +428,26 @@ uart2: serial@402bc000 {
>> status = "disabled";
>> };
>>
>> + i2c3: i2c@402d8000 {
>> + compatible = "nxp,s32g3-i2c",
>> + "nxp,s32g2-i2c";
>> + reg = <0x402d8000 0x1000>;
>> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> + i2c4: i2c@402dc000 {
>> + compatible = "nxp,s32g3-i2c",
>> + "nxp,s32g2-i2c";
>> + reg = <0x402dc000 0x1000>;
>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 40>;
>> + clock-names = "ipg";
>> + status = "disabled";
>> + };
>> +
>> usdhc0: mmc@402f0000 {
>> compatible = "nxp,s32g3-usdhc",
>> "nxp,s32g2-usdhc";
>> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
>> index 828e353455b5..5f8739c068c6 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
>> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
>> @@ -8,6 +8,7 @@
>> /dts-v1/;
>>
>> #include "s32g3.dtsi"
>> +#include "s32gxxxa-rdb.dtsi"
>>
>> / {
>> model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
>> @@ -39,6 +40,14 @@ &uart1 {
>> status = "okay";
>> };
>>
>> +&i2c4 {
>> + ina231@40 {
>> + compatible = "ti,ina231";
>> + reg = <0x40>;
>> + shunt-resistor = <1000>;
>> + };
>> +};
>> +
>> &usdhc0 {
>> pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> pinctrl-0 = <&pinctrl_usdhc0>;
>> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
>> new file mode 100644
>> index 000000000000..a44eff28073a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
>> @@ -0,0 +1,150 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright 2024 NXP
>> + *
>> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
>> + * Larisa Grigore <larisa.grigore@nxp.com>
>> + */
>> +
>> +&pinctrl {
>> + i2c0_pins: i2c0-pins {
>> + i2c0-grp0 {
>> + pinmux = <0x101>, <0x111>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c0-grp1 {
>> + pinmux = <0x2352>, <0x2362>;
>> + };
>> + };
>> +
>> + i2c0_gpio_pins: i2c0-gpio-pins {
>> + i2c0-gpio-grp0 {
>> + pinmux = <0x100>, <0x110>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c0-gpio-grp1 {
>> + pinmux = <0x2350>, <0x2360>;
>> + };
>> + };
>> +
>> + i2c1_pins: i2c1-pins {
>> + i2c1-grp0 {
>> + pinmux = <0x131>, <0x141>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c1-grp1 {
>> + pinmux = <0x2cd2>, <0x2ce2>;
>> + };
>> + };
>> +
>> + i2c1_gpio_pins: i2c1-gpio-pins {
>> + i2c1-gpio-grp0 {
>> + pinmux = <0x130>, <0x140>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c1-gpio-grp1 {
>> + pinmux = <0x2cd0>, <0x2ce0>;
>> + };
>> + };
>> +
>> + i2c2_pins: i2c2-pins {
>> + i2c2-grp0 {
>> + pinmux = <0x151>, <0x161>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c2-grp1 {
>> + pinmux = <0x2cf2>, <0x2d02>;
>> + };
>> + };
>> +
>> + i2c2_gpio_pins: i2c2-gpio-pins {
>> + i2c2-gpio-grp0 {
>> + pinmux = <0x150>, <0x160>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c2-gpio-grp1 {
>> + pinmux = <0x2cf0>, <0x2d00>;
>> + };
>> + };
>> +
>> + i2c4_pins: i2c4-pins {
>> + i2c4-grp0 {
>> + pinmux = <0x211>, <0x222>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c4-grp1 {
>> + pinmux = <0x2d43>, <0x2d33>;
>> + };
>> + };
>> +
>> + i2c4_gpio_pins: i2c4-gpio-pins {
>> + i2c4-gpio-grp0 {
>> + pinmux = <0x210>, <0x220>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c4-gpio-grp1 {
>> + pinmux = <0x2d40>, <0x2d30>;
>> + };
>> + };
>> +};
>> +
>> +&i2c0 {
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-1 = <&i2c0_gpio_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c1_pins>;
>> + pinctrl-1 = <&i2c1_gpio_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c2_pins>;
>> + pinctrl-1 = <&i2c2_gpio_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c4 {
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c4_pins>;
>> + pinctrl-1 = <&i2c4_gpio_pins>;
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>> new file mode 100644
>> index 000000000000..50fe6aaa1605
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>> @@ -0,0 +1,126 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright 2024 NXP
>> + *
>> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
>> + * Larisa Grigore <larisa.grigore@nxp.com>
>> + */
>> +
>> +&pinctrl {
>> + i2c0_pins: i2c0-pins {
>> + i2c0-grp0 {
>> + pinmux = <0x1f2>, <0x201>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c0-grp1 {
>> + pinmux = <0x2353>, <0x2363>;
>> + };
>> + };
>> +
>> + i2c0_gpio_pins: i2c0-gpio-pins {
>> + i2c0-gpio-grp0 {
>> + pinmux = <0x1f0>, <0x200>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c0-gpio-grp1 {
>> + pinmux = <0x2350>, <0x2360>;
>> + };
>> + };
>> +
>> + i2c2_pins: i2c2-pins {
>> + i2c2-grp0 {
>> + pinmux = <0x151>, <0x161>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c2-grp1 {
>> + pinmux = <0x2cf2>, <0x2d02>;
>> + };
>> + };
>> +
>> + i2c2_gpio_pins: i2c2-gpio-pins {
>> + i2c2-gpio-grp0 {
>> + pinmux = <0x2cf0>, <0x2d00>;
>> + };
>> +
>> + i2c2-gpio-grp1 {
>> + pinmux = <0x150>, <0x160>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> + };
>> +
>> + i2c4_pins: i2c4-pins {
>> + i2c4-grp0 {
>> + pinmux = <0x211>, <0x222>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c4-grp1 {
>> + pinmux = <0x2d43>, <0x2d33>;
>> + };
>> + };
>> +
>> + i2c4_gpio_pins: i2c4-gpio-pins {
>> + i2c4-gpio-grp0 {
>> + pinmux = <0x210>, <0x220>;
>> + drive-open-drain;
>> + output-enable;
>> + input-enable;
>> + slew-rate = <133>;
>> + };
>> +
>> + i2c4-gpio-grp1 {
>> + pinmux = <0x2d40>, <0x2d30>;
>> + };
>> + };
>> +};
>> +
>> +&i2c0 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>
> I remember I have said "#address-cells" and "#size-cells" should be in
> dtsi to avoid copy it at each board dts file.
>
> Frank
>
Yes, and I've moved them from board dts into a common board dtsi, which
is the newly added 's32gxxxa-rdb.dtsi' as per commit description. This
way I am not duplicating any such info in 's32g2.dtsi' and 's32g3.dtsi'.
Best Regards,
Ciprian
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-1 = <&i2c0_gpio_pins>;
>> + status = "okay";
>> +
>> + pcal6524: gpio-expander@22 {
>> + compatible = "nxp,pcal6524";
>> + reg = <0x22>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +};
>> +
>> +&i2c2 {
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c2_pins>;
>> + pinctrl-1 = <&i2c2_gpio_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c4 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default", "gpio";
>> + pinctrl-0 = <&i2c4_pins>;
>> + pinctrl-1 = <&i2c4_gpio_pins>;
>> + status = "okay";
>> +};
>> --
>> 2.45.2
>>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-12-19 8:12 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2024-12-13 14:22 [PATCH v2] arm64: dts: s32g: add I2C support Ciprian Costea
2024-12-13 19:15 ` Frank Li
2024-12-19 8:11 ` Ciprian Marian Costea
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