Re: [PATCH] mtd: spi-nor: add support for Microchip 25LC256

Radu Pirea
2018-05-18T09:49:14Z

On 05/16/2018 04:47 PM, Marek Vasut wrote:
> On 05/16/2018 12:05 PM, Radu Pirea wrote:
>> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
>>> On 05/15/2018 06:22 PM, Radu Pirea wrote:
>>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>>>>> On Fri, 4 May 2018 18:54:04 +0300
>>>>> Radu Pirea <radu.pirea@microchip.com> wrote:
>>>>>
>>>>>> Added geometry description for Microchip 25LC256 memory.
>>>>>
>>>>> Same as for the dataflash stuff you posted a few weeks ago: I
>>>>> don't
>>>>> think this device belongs in the SPI NOR framework.
>>>>
>>>> Hi Boris,
>>>>
>>>> 25lc256 memory is similar with mr25h256, the only difference is the
>>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR
>>>> framework
>>>> I added here 25lc256.
>>>
>>> I think I must be reading the wrong datasheet, but can you show me
>>> how
>>> does it support things like READID opcode ?
>>>
>> Hi Marek,
>>
>> I read the datasheet for 25lc256 and for mr25h256 and none of them
>> supports READID. Is this required for a chip to be included in spi-nor
>> framework? I just followed the mr25h256 as an example.
>
> So I thought until you pointed out the MR25 devices.
>
> Does the 25LC device need erase or not ? I think the MR25s didn't, but I
> might be wrong.

You are right. MR25s does not need erase and the same thing is true for
25LC.

>
> Maybe the framework could support the 25LC afterall.
>
Yes, this was my impression too.

Thanks.