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([2620:15c:2c1:200:55c7:81e6:c7d8:94b]) by smtp.gmail.com with ESMTPSA id ce16sm2742759pjb.29.2019.10.09.09.39.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2019 09:39:43 -0700 (PDT) Subject: Re: Kernel Concurrency Sanitizer (KCSAN) To: Dmitry Vyukov , Eric Dumazet Cc: Will Deacon , Marco Elver , kasan-dev , LKML , Andrey Konovalov , Alexander Potapenko , "Paul E. McKenney" , Paul Turner , Daniel Axtens , Anatol Pomazau , Andrea Parri , Alan Stern , LKMM Maintainers -- Akira Yokosawa , Nicholas Piggin , Boqun Feng , Daniel Lustig , Jade Alglave , Luc Maranget References: <20190920155420.rxiflqdrpzinncpy@willie-the-truck> <0715d98b-12e9-fd81-31d1-67bcb752b0a1@gmail.com> From: Eric Dumazet Message-ID: Date: Wed, 9 Oct 2019 09:39:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/9/19 12:45 AM, Dmitry Vyukov wrote: > On Sat, Oct 5, 2019 at 6:16 AM Dmitry Vyukov wrote: >> >> On Sat, Oct 5, 2019 at 2:58 AM Eric Dumazet wrote: >>>> This one is tricky. What I think we need to avoid is an onslaught of >>>> patches adding READ_ONCE/WRITE_ONCE without a concrete analysis of the >>>> code being modified. My worry is that Joe Developer is eager to get their >>>> first patch into the kernel, so runs this tool and starts spamming >>>> maintainers with these things to the point that they start ignoring KCSAN >>>> reports altogether because of the time they take up. >>>> >>>> I suppose one thing we could do is to require each new READ_ONCE/WRITE_ONCE >>>> to have a comment describing the racy access, a bit like we do for memory >>>> barriers. Another possibility would be to use atomic_t more widely if >>>> there is genuine concurrency involved. >>>> >>> >>> About READ_ONCE() and WRITE_ONCE(), we will probably need >>> >>> ADD_ONCE(var, value) for arches that can implement the RMW in a single instruction. >>> >>> WRITE_ONCE(var, var + value) does not look pretty, and increases register pressure. >> >> FWIW modern compilers can handle this if we tell them what we are trying to do: >> >> void foo(int *p, int x) >> { >> x += __atomic_load_n(p, __ATOMIC_RELAXED); >> __atomic_store_n(p, x, __ATOMIC_RELAXED); >> } >> >> $ clang test.c -c -O2 && objdump -d test.o >> >> 0000000000000000 : >> 0: 01 37 add %esi,(%rdi) >> 2: c3 retq >> >> We can have syntactic sugar on top of this of course. > > An interesting precedent come up in another KCSAN bug report. Namely, > it may be reasonable for a compiler to use different optimization > heuristics for concurrent and non-concurrent code. Consider there are > some legal code transformations, but it's unclear if they are > profitable or not. It may be the case that for non-concurrent code the > expectation is that it's a profitable transformation, but for > concurrent code it is not. So that may be another reason to > communicate to compiler what we want to do, rather than trying to > trick and play against each other. I've added the concrete example > here: > https://github.com/google/ktsan/wiki/READ_ONCE-and-WRITE_ONCE#it-may-improve-performance > Note that for bit fields, READ_ONCE() wont work. Concrete example in net/xfrm/xfrm_algo.c:xfrm_probe_algs(void) ... if (aalg_list[i].available != status) aalg_list[i].available = status; ... if (ealg_list[i].available != status) ealg_list[i].available = status; ... if (calg_list[i].available != status) calg_list[i].available = status;