Re: [PATCH 8/8] media: iris: Add platform data for kaanapali

Vishnu Reddy
2025-10-18T06:56:22Z

On 10/2/2025 8:59 PM, Bryan O'Donoghue wrote:
> On 25/09/2025 00:14, Vikash Garodia wrote:
>> Add support for the kaanapali platform by re-using the SM8550
>> definitions and using the vpu4 ops.
>> Move the configurations that differs in a per-SoC platform
>> header, that will contain SoC specific data.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>>   .../platform/qcom/iris/iris_platform_common.h      |  1 +
>>   .../media/platform/qcom/iris/iris_platform_gen2.c  | 86
>> ++++++++++++++++++++++
>>   .../platform/qcom/iris/iris_platform_kaanapali.h   | 63
>> ++++++++++++++++
>>   drivers/media/platform/qcom/iris/iris_probe.c      |  4 +
>>   4 files changed, 154 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> index
>> d6d4a9fdfc189797f903dfeb56d931741b405ee2..465943db0c6671e9b564b40e31ce6ba2d645a84c 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> @@ -46,6 +46,7 @@ extern struct iris_platform_data sm8250_data;
>>   extern struct iris_platform_data sm8550_data;
>>   extern struct iris_platform_data sm8650_data;
>>   extern struct iris_platform_data sm8750_data;
>> +extern struct iris_platform_data kaanapali_data;
>>
>>   enum platform_clk_type {
>>       IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI
>> clocks */
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> index
>> 00c6b9021b98aac80612b1bb9734c8dac8146bd9..142b7d84ee00a9b65420158ac1f168515b56f4a3 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> @@ -15,6 +15,7 @@
>>   #include "iris_platform_qcs8300.h"
>>   #include "iris_platform_sm8650.h"
>>   #include "iris_platform_sm8750.h"
>> +#include "iris_platform_kaanapali.h"
>>
>>   #define VIDEO_ARCH_LX 1
>>   #define BITRATE_MAX                245000000
>> @@ -1095,3 +1096,88 @@ struct iris_platform_data qcs8300_data = {
>>       .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>>       .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>>   };
>> +
>> +struct iris_platform_data kaanapali_data = {
>> +    .get_instance = iris_hfi_gen2_get_instance,
>> +    .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>> +    .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
>> +    .get_vpu_buffer_size = iris_vpu4x_buf_size,
>> +    .vpu_ops = &iris_vpu4x_ops,
>> +    .set_preset_registers = iris_set_sm8550_preset_registers,
>> +    .icc_tbl = sm8550_icc_table,
>> +    .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
>> +    .clk_rst_tbl = kaanapali_clk_reset_table,
>> +    .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table),
>> +    .bw_tbl_dec = sm8550_bw_table_dec,
>> +    .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
>> +    .pmdomain_tbl = kaanapali_pmdomain_table,
>> +    .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table),
>> +    .opp_pd_tbl = sm8550_opp_pd_table,
>> +    .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> +    .clk_tbl = kaanapali_clk_table,
>> +    .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table),
>> +    .opp_clk_tbl = kaanapali_opp_clk_table,
>> +    /* Upper bound of DMA address range */
>> +    .dma_mask = 0xe0000000 - 1,
>> +    .fwname = "qcom/vpu/vpu40_p2.mbn",
>> +    .pas_id = IRIS_PAS_ID,
>> +    .inst_caps = &platform_inst_cap_sm8550,
>> +    .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
>> +    .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
>> +    .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
>> +    .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>> +    .tz_cp_config_data = tz_cp_config_kaanapali,
>> +    .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali),
>> +    .core_arch = VIDEO_ARCH_LX,
>> +    .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> +    .ubwc_config = &ubwc_config_sm8550,
>> +    .num_vpp_pipe = 2,
>> +    .max_session_count = 16,
>> +    .max_core_mbpf = NUM_MBS_8K * 2,
>> +    .max_core_mbps = ((8192 * 4352) / 256) * 60,
>> +    .dec_input_config_params_default =
>> +        sm8550_vdec_input_config_params_default,
>> +    .dec_input_config_params_default_size =
>> +        ARRAY_SIZE(sm8550_vdec_input_config_params_default),
>> +    .dec_input_config_params_hevc =
>> +        sm8550_vdec_input_config_param_hevc,
>> +    .dec_input_config_params_hevc_size =
>> +        ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
>> +    .dec_input_config_params_vp9 =
>> +        sm8550_vdec_input_config_param_vp9,
>> +    .dec_input_config_params_vp9_size =
>> +        ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
>> +    .dec_output_config_params =
>> +        sm8550_vdec_output_config_params,
>> +    .dec_output_config_params_size =
>> +        ARRAY_SIZE(sm8550_vdec_output_config_params),
>> +
>> +    .enc_input_config_params =
>> +        sm8550_venc_input_config_params,
>> +    .enc_input_config_params_size =
>> +        ARRAY_SIZE(sm8550_venc_input_config_params),
>> +    .enc_output_config_params =
>> +        sm8550_venc_output_config_params,
>> +    .enc_output_config_params_size =
>> +        ARRAY_SIZE(sm8550_venc_output_config_params),
>> +
>> +    .dec_input_prop = sm8550_vdec_subscribe_input_properties,
>> +    .dec_input_prop_size =
>> ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
>> +    .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
>> +    .dec_output_prop_avc_size =
>> +        ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
>> +    .dec_output_prop_hevc =
>> sm8550_vdec_subscribe_output_properties_hevc,
>> +    .dec_output_prop_hevc_size =
>> +        ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
>> +    .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
>> +    .dec_output_prop_vp9_size =
>> +        ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
>> +
>> +    .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
>> +    .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
>> +    .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
>> +    .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
>> +
>> +    .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>> +    .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>> +};
>> diff --git
>> a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
>> b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..247fb9d7cb632d2e9a1e9832d087cb03ac9b7cf3
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
>> @@ -0,0 +1,63 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +#ifndef __IRIS_PLATFORM_KAANAPALI_H__
>> +#define __IRIS_PLATFORM_KAANAPALI_H__
>> +
>> +#define VIDEO_REGION_VM0_SECURE_NP_ID        1
>> +#define VIDEO_REGION_VM0_NONSECURE_NP_ID    5
>> +
>> +static const char *const kaanapali_clk_reset_table[] = {
>> +    "bus0",
>> +    "bus1",
>> +    "core_freerun_reset",
>> +    "vcodec0_core_freerun_reset",
>> +};
>> +
>> +static const char *const kaanapali_pmdomain_table[] = {
>> +    "venus",
>> +    "vcodec0",
>> +    "vpp0",
>> +    "vpp1",
>> +    "apv",
>> +};
>> +
>> +static const struct platform_clk_data kaanapali_clk_table[] = {
>> +    { IRIS_AXI_CLK, "iface" },
>> +    { IRIS_CTRL_CLK, "core" },
>> +    { IRIS_HW_CLK, "vcodec0_core" },
>> +    { IRIS_AXI1_CLK, "iface1" },
>> +    { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
>> +    { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
>> +    { IRIS_BSE_HW_CLK, "vcodec_bse" },
>> +    { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
>> +    { IRIS_VPP1_HW_CLK, "vcodec_vpp1" },
>> +    { IRIS_APV_HW_CLK, "vcodec_apv" },
>> +};
>> +
>> +static const char *const kaanapali_opp_clk_table[] = {
>> +    "vcodec0_core",
>> +    "vcodec_apv",
>> +    "vcodec_bse",
>> +    "core",
>> +    NULL,
>> +};
>
> Why are mxc and mmcx absett from this table ?
>
> ---
> bod

mxc and mmcx OPP power domains listed in opp_pd_table
(sm8550_opp_pd_table in iris_platform_gen2.c). This opp_pd_tbl list
attached with PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP when calling
devm_pm_domain_attach_list, while pmdomain_tbl list will be attached
with PD_FLAG_NO_DEV_LINK flag.

Regards,
Vishnu Reddy