From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>
Cc: baolu.lu@linux.intel.com, "Raj, Ashok" <ashok.raj@intel.com>,
"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
"Sun, Yi Y" <yi.y.sun@intel.com>,
"peterx@redhat.com" <peterx@redhat.com>,
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: Re: [PATCH v4 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support
Date: Thu, 8 Nov 2018 10:16:51 +0800 [thread overview]
Message-ID: <a6e43ddd-0889-4a4a-b908-993db28c6d87@linux.intel.com> (raw)
In-Reply-To: <A2975661238FB949B60364EF0F2C257439D5FAA2@SHSMSX104.ccr.corp.intel.com>
Hi Yi,
On 11/7/18 2:07 PM, Liu, Yi L wrote:
> Hi Baolu,
>
>> From: Lu Baolu [mailto:baolu.lu@linux.intel.com]
>> Sent: Monday, November 5, 2018 1:32 PM
>
> [...]
>
>> ---
>> drivers/iommu/dmar.c | 83 +++++++++++++++++++----------
>> drivers/iommu/intel-svm.c | 76 ++++++++++++++++----------
>> drivers/iommu/intel_irq_remapping.c | 6 ++-
>> include/linux/intel-iommu.h | 9 +++-
>> 4 files changed, 115 insertions(+), 59 deletions(-)
>>
>> diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
>> index d9c748b6f9e4..ec10427b98ac 100644
>> --- a/drivers/iommu/dmar.c
>> +++ b/drivers/iommu/dmar.c
>> @@ -1160,6 +1160,7 @@ static int qi_check_fault(struct intel_iommu *iommu, int
>> index)
>> int head, tail;
>> struct q_inval *qi = iommu->qi;
>> int wait_index = (index + 1) % QI_LENGTH;
>> + int shift = qi_shift(iommu);
>>
>> if (qi->desc_status[wait_index] == QI_ABORT)
>> return -EAGAIN;
>> @@ -1173,13 +1174,15 @@ static int qi_check_fault(struct intel_iommu *iommu,
>> int index)
>> */
>> if (fault & DMA_FSTS_IQE) {
>> head = readl(iommu->reg + DMAR_IQH_REG);
>> - if ((head >> DMAR_IQ_SHIFT) == index) {
>> + if ((head >> shift) == index) {
>> + struct qi_desc *desc = qi->desc + head;
>> +
>> pr_err("VT-d detected invalid descriptor: "
>> "low=%llx, high=%llx\n",
>> - (unsigned long long)qi->desc[index].low,
>> - (unsigned long long)qi->desc[index].high);
>> - memcpy(&qi->desc[index], &qi->desc[wait_index],
>> - sizeof(struct qi_desc));
>> + (unsigned long long)desc->qw0,
>> + (unsigned long long)desc->qw1);
>
> Still missing qw2 and qw3. May make the print differ based on if smts is configed.
qw2 and qw3 are reserved from software point of view. We don't need to
print it for information.
>
>> + memcpy(desc, qi->desc + (wait_index << shift),
>
> Would "memcpy(desc, (unsigned long long) (qi->desc + (wait_index << shift)," be
> more safe?
Can that be compiled? memcpy() requires a "const void *" for the second
parameter. By the way, why it's safer with this casting?
>
>> + 1 << shift);
>> writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
>> return -EINVAL;
>> }
>> @@ -1191,10 +1194,10 @@ static int qi_check_fault(struct intel_iommu *iommu,
>> int index)
>> */
>> if (fault & DMA_FSTS_ITE) {
>> head = readl(iommu->reg + DMAR_IQH_REG);
>> - head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
>> + head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
>> head |= 1;
>> tail = readl(iommu->reg + DMAR_IQT_REG);
>> - tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
>> + tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
>>
>> writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
>>
>> @@ -1222,15 +1225,14 @@ int qi_submit_sync(struct qi_desc *desc, struct
>> intel_iommu *iommu)
>> {
>> int rc;
>> struct q_inval *qi = iommu->qi;
>> - struct qi_desc *hw, wait_desc;
>> + int offset, shift, length;
>> + struct qi_desc wait_desc;
>> int wait_index, index;
>> unsigned long flags;
>>
>> if (!qi)
>> return 0;
>>
>> - hw = qi->desc;
>> -
>> restart:
>> rc = 0;
>>
>> @@ -1243,16 +1245,21 @@ int qi_submit_sync(struct qi_desc *desc, struct
>> intel_iommu *iommu)
>>
>> index = qi->free_head;
>> wait_index = (index + 1) % QI_LENGTH;
>> + shift = qi_shift(iommu);
>> + length = 1 << shift;
>>
>> qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
>>
>> - hw[index] = *desc;
>> -
>> - wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
>> + offset = index << shift;
>> + memcpy(qi->desc + offset, desc, length);
>> + wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
>> QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
>> - wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
>> + wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
>> + wait_desc.qw2 = 0;
>> + wait_desc.qw3 = 0;
>>
>> - hw[wait_index] = wait_desc;
>> + offset = wait_index << shift;
>> + memcpy(qi->desc + offset, &wait_desc, length);
>
> same question with above one.
>
Ditto.
Best regards,
Lu Baolu
next prev parent reply other threads:[~2018-11-08 2:19 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-05 5:31 [PATCH v4 00/12] iommu/vt-d: Add scalable mode support Lu Baolu
2018-11-05 5:31 ` [PATCH v4 01/12] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-11-05 5:31 ` [PATCH v4 02/12] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-11-05 5:31 ` [PATCH v4 03/12] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-11-07 7:41 ` Liu, Yi L
2018-11-05 5:31 ` [PATCH v4 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support Lu Baolu
2018-11-07 6:07 ` Liu, Yi L
2018-11-08 2:16 ` Lu Baolu [this message]
2018-11-08 3:49 ` Liu, Yi L
2018-11-08 5:24 ` Lu Baolu
2018-11-08 5:45 ` Liu, Yi L
2018-11-08 6:14 ` Lu Baolu
2018-11-08 7:20 ` Liu, Yi L
2018-11-09 1:39 ` Lu Baolu
2018-11-09 2:59 ` Liu, Yi L
2018-11-08 5:48 ` Liu, Yi L
2018-11-08 6:15 ` Lu Baolu
2018-11-05 5:31 ` [PATCH v4 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes Lu Baolu
2018-11-07 6:55 ` Liu, Yi L
2018-11-08 2:22 ` Lu Baolu
2018-11-05 5:31 ` [PATCH v4 06/12] iommu/vt-d: Add second level page table interface Lu Baolu
2018-11-07 7:13 ` Liu, Yi L
2018-11-08 2:27 ` Lu Baolu
2018-11-08 4:00 ` Liu, Yi L
2018-11-05 5:31 ` [PATCH v4 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support Lu Baolu
2018-11-05 5:31 ` [PATCH v4 08/12] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-11-07 7:25 ` Liu, Yi L
2018-11-08 2:34 ` Lu Baolu
2018-11-05 5:31 ` [PATCH v4 09/12] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-11-05 5:31 ` [PATCH v4 10/12] iommu/vt-d: Add first level page table interface Lu Baolu
2018-11-07 7:34 ` Liu, Yi L
2018-11-05 5:31 ` [PATCH v4 11/12] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-11-05 7:15 ` Christoph Hellwig
2018-11-05 7:17 ` Lu Baolu
2018-11-05 5:31 ` [PATCH v4 12/12] iommu/vt-d: Remove deferred invalidation Lu Baolu
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