[PATCH 0/5] Add components to support PQ in display path for MT8196

[PATCH 0/5] Add components to support PQ in display path for MT8196

[Sunny Shen]

Due to the path mux design of the MT8196, the following components need to be configured to support Picture Quality (PQ) in the display path:CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.

This patch series is based on [1]
[1] Add Mediatek Soc DRM Soc support for mt8196
    - https://patchwork.kernel.org/project/linux-mediatek/list/?series=924191

Sunny Shen (5):
  dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196
  dt-bindings: display: mediatek: postmask: Modify rules for MT8196
  soc: mediatek: Add components to support PQ in display path for MT8196
  drm/mediatek: Add MDP-RSZ component support for MT8196
  drm/mediatek: Change main display path to support PQ for MT8196

 .../display/mediatek/mediatek,mdp-rsz.yaml    | 46 ++++++++++++
 .../display/mediatek/mediatek,postmask.yaml   |  1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       | 24 +++++++
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h       |  1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  9 +++
 drivers/soc/mediatek/mt8196-mmsys.h           | 70 ++++++++++++++++++-
 drivers/soc/mediatek/mtk-mutex.c              | 17 +++++
 include/linux/soc/mediatek/mtk-mmsys.h        |  5 ++
 8 files changed, 171 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml

-- 
2.34.1

[PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Sunny Shen]

Add MDP-RSZ hardware description for MediaTek MT8196 SoC

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 .../display/mediatek/mediatek,mdp-rsz.yaml    | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
new file mode 100644
index 000000000000..6642b9aa651a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek display multimedia data path resizer
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  MediaTek display multimedia data path resizer, namely MDP-RSZ,
+  can do scaling up/down to the picture.
+
+properties:
+  compatible:
+    const: mediatek,mt8196-disp-mdp-rsz
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: MDP-RSZ Clock
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
+            compatible = "mediatek,mt8196-disp-mdp-rsz";
+            reg = <0 0x321a0000 0 0x1000>;
+            clocks = <&dispsys_config_clk 101>;
+        };
+    };
-- 
2.34.1

[PATCH 2/5] dt-bindings: display: mediatek: postmask: Modify rules for MT8196

[Sunny Shen]

Add a compatible string for MediaTek MT8196 SoC

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,postmask.yaml  | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
index fb6fe4742624..29624ac191e1 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
@@ -27,6 +27,7 @@ properties:
           - enum:
               - mediatek,mt8186-disp-postmask
               - mediatek,mt8188-disp-postmask
+              - mediatek,mt8196-disp-postmask
           - const: mediatek,mt8192-disp-postmask
 
   reg:
-- 
2.34.1

[PATCH 3/5] soc: mediatek: Add components to support PQ in display path for MT8196

[Sunny Shen]

Due to the path mux design of the MT8196, the following components
need to be configured into mutex and mmsys to support
Picture Quality (PQ) in the display path:CCORR0, CCORR1, DITHER0,
GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 drivers/soc/mediatek/mt8196-mmsys.h    | 70 +++++++++++++++++++++++++-
 drivers/soc/mediatek/mtk-mutex.c       | 17 +++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  5 ++
 3 files changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mt8196-mmsys.h b/drivers/soc/mediatek/mt8196-mmsys.h
index 03d1210d2b80..b686d5029219 100644
--- a/drivers/soc/mediatek/mt8196-mmsys.h
+++ b/drivers/soc/mediatek/mt8196-mmsys.h
@@ -68,6 +68,22 @@
 #define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY7		BIT(2)
 
 /* DISPSYS0 */
+#define MT8196_DISP_CCORR0_SEL				0xd28
+#define MT8196_DISP_CCORR0_FROM_TDSHP0				BIT(1)
+#define MT8196_DISP_CCORR0_SOUT				0xd2c
+#define MT8196_DISP_CCORR0_TO_CCORR1				BIT(0)
+#define MT8196_DISP_CCORR1_SEL				0xd30
+#define MT8196_DISP_CCORR1_FROM_CCORR0				BIT(0)
+#define MT8196_DISP_CCORR1_SOUT				0xd34
+#define MT8196_DISP_CCORR1_TO_GAMMA0				BIT(0)
+#define MT8196_DISP_GAMMA0_SEL				0xd58
+#define MT8196_DISP_GAMMA0_FROM_CCORR1				BIT(0)
+#define MT8196_DISP_POSTMASK0_SOUT			0xd68
+#define MT8196_DISP_POSTMASK0_TO_DITHER0			0x0
+#define MT8196_DISP_TDSHP0_SOUT				0xd70
+#define MT8196_DISP_TDSHP0_TO_CCORR0				BIT(1)
+#define MT8196_MDP_RSZ0_MOUT_EN				0xd78
+#define MT8196_MDP_RSZ0_TO_TDSHP0				BIT(0)
 #define MT8196_PANEL_COMP_OUT_CB1_MOUT_EN		0xd84
 #define MT8196_DISP_TO_DLO_RELAY1				BIT(1)
 #define MT8196_PANEL_COMP_OUT_CB2_MOUT_EN		0xd88
@@ -75,12 +91,14 @@
 #define MT8196_PANEL_COMP_OUT_CB3_MOUT_EN		0xd8c
 #define MT8196_DISP_TO_DLO_RELAY3				BIT(3)
 #define MT8196_PQ_IN_CB0_MOUT_EN			0xdd0
+#define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0				BIT(0)
 #define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6				BIT(2)
-
 #define MT8196_PQ_IN_CB1_MOUT_EN			0xdd4
 #define MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7				BIT(3)
 #define MT8196_PQ_IN_CB8_MOUT_EN			0xdf0
 #define MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8				BIT(4)
+#define MT8196_PQ_OUT_CB0_MOUT_EN			0xe3c
+#define MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1		BIT(1)
 #define MT8196_PQ_OUT_CB6_MOUT_EN			0xe54
 #define MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1		BIT(1)
 #define MT8196_PQ_OUT_CB7_MOUT_EN			0xe58
@@ -314,11 +332,13 @@ static const struct mtk_mmsys_routes mmsys_mt8196_ovl1_routing_table[] = {
 };
 
 /*
- * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ_OUT_CB6 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1
+ * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ (MDP_RSZ0/TDSHP0/CCORR0/CCORR1/GAMMA0/POSTMASK0/DITHER0)
+ *       -> PQ_OUT_CB0 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1
  * ext:  DLI_ASYNC1-> PQ_IN_CB1 -> PQ_OUT_CB7 -> PANEL_COMP_OUT_CB2 -> DLO_ASYNC2
  */
 static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = {
 	{
+	/* main: PQ bypass */
 		DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_DLO_ASYNC1,
 		MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6,
 		MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6
@@ -331,6 +351,52 @@ static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = {
 		MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1,
 		MT8196_DISP_TO_DLO_RELAY1
 	}, {
+	/* main: PQ path */
+		DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_MDP_RSZ0,
+		MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0,
+		MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0
+	}, {
+		DDP_COMPONENT_MDP_RSZ0, DDP_COMPONENT_TDSHP0,
+		MT8196_MDP_RSZ0_MOUT_EN, MT8196_MDP_RSZ0_TO_TDSHP0,
+		MT8196_MDP_RSZ0_TO_TDSHP0
+	}, {
+		DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0,
+		MT8196_DISP_TDSHP0_SOUT, MT8196_DISP_TDSHP0_TO_CCORR0,
+		MT8196_DISP_TDSHP0_TO_CCORR0
+	}, {
+		DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0,
+		MT8196_DISP_CCORR0_SEL, MT8196_DISP_CCORR0_FROM_TDSHP0,
+		MT8196_DISP_CCORR0_FROM_TDSHP0
+	}, {
+		DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1,
+		MT8196_DISP_CCORR0_SOUT, MT8196_DISP_CCORR0_TO_CCORR1,
+		MT8196_DISP_CCORR0_TO_CCORR1
+	}, {
+		DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1,
+		MT8196_DISP_CCORR1_SEL, MT8196_DISP_CCORR1_FROM_CCORR0,
+		MT8196_DISP_CCORR1_FROM_CCORR0
+	}, {
+		DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0,
+		MT8196_DISP_CCORR1_SOUT, MT8196_DISP_CCORR1_TO_GAMMA0,
+		MT8196_DISP_CCORR1_TO_GAMMA0
+	}, {
+		DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0,
+		MT8196_DISP_GAMMA0_SEL, MT8196_DISP_GAMMA0_FROM_CCORR1,
+		MT8196_DISP_GAMMA0_FROM_CCORR1
+	}, {
+		DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_DITHER0,
+		MT8196_DISP_POSTMASK0_SOUT, MT8196_DISP_POSTMASK0_TO_DITHER0,
+		MT8196_DISP_POSTMASK0_TO_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1,
+		MT8196_PQ_OUT_CB0_MOUT_EN, MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1,
+		MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1
+	}, {
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1,
+		MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1,
+		MT8196_DISP_TO_DLO_RELAY1
+	}, {
+	/* ext */
 		DDP_COMPONENT_DLI_ASYNC1, DDP_COMPONENT_DLO_ASYNC2,
 		MT8196_PQ_IN_CB1_MOUT_EN, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7,
 		MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 51db6f2a05ae..9c895566dfb2 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -262,6 +262,11 @@
 #define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6	(32 + 17)
 
 /* DISP0 */
+
+#define MT8196_MUTEX_MOD0_DISP_CCORR0		6
+#define MT8196_MUTEX_MOD0_DISP_CCORR1		7
+#define MT8196_MUTEX_MOD0_DISP_DITHER0		14
+
 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0	16
 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1	17
 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8	24
@@ -269,6 +274,11 @@
 #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2	(32 + 2)
 #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3	(32 + 3)
 
+#define MT8196_MUTEX_MOD1_DISP_GAMMA0		(32 + 9)
+#define MT8196_MUTEX_MOD1_DISP_POSTMASK0	(32 + 14)
+#define MT8196_MUTEX_MOD1_DISP_MDP_RSZ0		(32 + 18)
+#define MT8196_MUTEX_MOD1_DISP_TDSHP0		(32 + 21)
+
 /* DISP1 */
 #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21	1
 #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22	2
@@ -678,6 +688,13 @@ static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
 };
 
 static const u8 mt8196_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_CCORR0] = MT8196_MUTEX_MOD0_DISP_CCORR0,
+	[DDP_COMPONENT_CCORR1] = MT8196_MUTEX_MOD0_DISP_CCORR1,
+	[DDP_COMPONENT_DITHER0] = MT8196_MUTEX_MOD0_DISP_DITHER0,
+	[DDP_COMPONENT_GAMMA0] = MT8196_MUTEX_MOD1_DISP_GAMMA0,
+	[DDP_COMPONENT_MDP_RSZ0] = MT8196_MUTEX_MOD1_DISP_MDP_RSZ0,
+	[DDP_COMPONENT_POSTMASK0] = MT8196_MUTEX_MOD1_DISP_POSTMASK0,
+	[DDP_COMPONENT_TDSHP0] = MT8196_MUTEX_MOD1_DISP_TDSHP0,
 	[DDP_COMPONENT_OVL0_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2,
 	[DDP_COMPONENT_OVL0_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3,
 	[DDP_COMPONENT_OVL0_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4a0b10567581..250054ca5523 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -25,6 +25,8 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_AAL1,
 	DDP_COMPONENT_BLS,
 	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_CCORR0 = DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_CCORR1,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER0,
@@ -51,6 +53,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_DVO0,
 	DDP_COMPONENT_ETHDR_MIXER,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_GAMMA0 = DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_MDP_RDMA0,
 	DDP_COMPONENT_MDP_RDMA1,
 	DDP_COMPONENT_MDP_RDMA2,
@@ -59,6 +62,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_MDP_RDMA5,
 	DDP_COMPONENT_MDP_RDMA6,
 	DDP_COMPONENT_MDP_RDMA7,
+	DDP_COMPONENT_MDP_RSZ0,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_MERGE1,
 	DDP_COMPONENT_MERGE2,
@@ -130,6 +134,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_RDMA1,
 	DDP_COMPONENT_RDMA2,
 	DDP_COMPONENT_RDMA4,
+	DDP_COMPONENT_TDSHP0,
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
-- 
2.34.1

[PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196

[Sunny Shen]

Add MDP-RSZ component support for MT8196.

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
 3 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 7f09a8977965..65878d3fe8a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -46,6 +46,10 @@
 #define DSC_BYPASS				BIT(4)
 #define DSC_UFOE_SEL				BIT(16)
 
+#define DISP_REG_MDP_RSZ_EN			0x0000
+#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
+#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
 	writel(1, priv->regs + DISP_REG_OD_EN);
 }
 
+static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
+			       unsigned int h, unsigned int vrefresh,
+			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MDP_RSZ_INPUT_SIZE);
+	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
+}
+
 static void mtk_postmask_config(struct device *dev, unsigned int w,
 				unsigned int h, unsigned int vrefresh,
 				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
 	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_mdp_rsz_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_postmask = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -454,6 +476,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
 	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,			2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,			3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,		0, &ddp_gamma },
+	[DDP_COMPONENT_MDP_RSZ0]	= { MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
 	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,		0, &ddp_merge },
 	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,		1, &ddp_merge },
 	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,		2, &ddp_merge },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index badb42bd4f7c..87f573fcc903 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_OVLSYS_ADAPTOR,
 	MTK_DISP_OVL_2L,
 	MTK_DISP_OVL_ADAPTOR,
+	MTK_DISP_MDP_RSZ,
 	MTK_DISP_POSTMASK,
 	MTK_DISP_PWM,
 	MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 50f5f81a7da1..b810a197f58b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -885,6 +885,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8195-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
+	  .data = (void *)MTK_DISP_MDP_RSZ },
 	{ .compatible = "mediatek,mt8195-disp-merge",
 	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
-- 
2.34.1

[PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196

[Sunny Shen]

Due to the path mux design of the MT8196, the following components
need to be added to support Picture Quality (PQ) in the main display
path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b810a197f58b..1c97dc46ae70 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
 
 static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
 	DDP_COMPONENT_DLI_ASYNC0,
+	DDP_COMPONENT_MDP_RSZ0,
+	DDP_COMPONENT_TDSHP0,
+	DDP_COMPONENT_CCORR0,
+	DDP_COMPONENT_CCORR1,
+	DDP_COMPONENT_GAMMA0,
+	DDP_COMPONENT_POSTMASK0,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DLO_ASYNC1,
 };
 
-- 
2.34.1

Re: [PATCH 2/5] dt-bindings: display: mediatek: postmask: Modify rules for MT8196

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1004 bytes --]

On Tue, Feb 11, 2025 at 10:52:51AM +0800, Sunny Shen wrote:
> Add a compatible string for MediaTek MT8196 SoC

$subject and $body don't match here.

> 
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,postmask.yaml  | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> index fb6fe4742624..29624ac191e1 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> @@ -27,6 +27,7 @@ properties:
>            - enum:
>                - mediatek,mt8186-disp-postmask
>                - mediatek,mt8188-disp-postmask
> +              - mediatek,mt8196-disp-postmask
>            - const: mediatek,mt8192-disp-postmask
>  
>    reg:
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2176 bytes --]

On Tue, Feb 11, 2025 at 10:52:50AM +0800, Sunny Shen wrote:
> Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> 
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
>  .../display/mediatek/mediatek,mdp-rsz.yaml    | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> new file mode 100644
> index 000000000000..6642b9aa651a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml#

Filename matching compatible please

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek display multimedia data path resizer
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  MediaTek display multimedia data path resizer, namely MDP-RSZ,
> +  can do scaling up/down to the picture.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8196-disp-mdp-rsz
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: MDP-RSZ Clock

This can just be "maxItems: 1"

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {

And "disp-mdp-rsz0" isn't anything close to a generic node name.

> +            compatible = "mediatek,mt8196-disp-mdp-rsz";
> +            reg = <0 0x321a0000 0 0x1000>;
> +            clocks = <&dispsys_config_clk 101>;

Surprised there are so few properties, no ports link or anything like
that?

> +        };
> +    };
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[CK Hu (胡俊光)]

On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> 
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
>  .../display/mediatek/mediatek,mdp-rsz.yaml    | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> new file mode 100644
> index 000000000000..6642b9aa651a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!jo9-Ezn5GR8wfDCMX72zrrpxlMEYb-5w52TYinNWsQlfpiPjw5R967JIU0-6WnI5fvIU7-v0IVaRALBlW4aL$ 
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jo9-Ezn5GR8wfDCMX72zrrpxlMEYb-5w52TYinNWsQlfpiPjw5R967JIU0-6WnI5fvIU7-v0IVaRAIIMW8TJ$ 
> +
> +title: MediaTek display multimedia data path resizer
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  MediaTek display multimedia data path resizer, namely MDP-RSZ,
> +  can do scaling up/down to the picture.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8196-disp-mdp-rsz

Reference to other display mdp device compatible, use

mediatek,mt8196-mdp-rsz

Regards,
CK

> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: MDP-RSZ Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> +            compatible = "mediatek,mt8196-disp-mdp-rsz";
> +            reg = <0 0x321a0000 0 0x1000>;
> +            clocks = <&dispsys_config_clk 101>;
> +        };
> +    };

Re: [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196

[CK Hu (胡俊光)]

On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> Add MDP-RSZ component support for MT8196.
> 
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
>  3 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index 7f09a8977965..65878d3fe8a9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -46,6 +46,10 @@
>  #define DSC_BYPASS				BIT(4)
>  #define DSC_UFOE_SEL				BIT(16)
>  
> +#define DISP_REG_MDP_RSZ_EN			0x0000

Do you config resizer in bypass mode so you need not to enable it?

> +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> +
>  #define DISP_REG_OD_EN				0x0000
>  #define DISP_REG_OD_CFG				0x0020
>  #define OD_RELAYMODE				BIT(0)
> @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
>  	writel(1, priv->regs + DISP_REG_OD_EN);
>  }
>  
> +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> +			       unsigned int h, unsigned int vrefresh,
> +			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);

Do you config resizer in bypass mode so width and height is set to zero?

Regards,
CK

> +}
> +
>  static void mtk_postmask_config(struct device *dev, unsigned int w,
>  				unsigned int h, unsigned int vrefresh,
>  				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
>  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> +	.clk_enable = mtk_ddp_clk_enable,
> +	.clk_disable = mtk_ddp_clk_disable,
> +	.config = mtk_mdp_rsz_config,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_postmask = {
>  	.clk_enable = mtk_ddp_clk_enable,
>  	.clk_disable = mtk_ddp_clk_disable,
> @@ -454,6 +476,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>  	[MTK_DISP_DITHER] = "dither",
>  	[MTK_DISP_DSC] = "dsc",
>  	[MTK_DISP_GAMMA] = "gamma",
> +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
>  	[MTK_DISP_MERGE] = "merge",
>  	[MTK_DISP_MUTEX] = "mutex",
>  	[MTK_DISP_OD] = "od",
> @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
>  	[DDP_COMPONENT_DSI2]		= { MTK_DSI,			2, &ddp_dsi },
>  	[DDP_COMPONENT_DSI3]		= { MTK_DSI,			3, &ddp_dsi },
>  	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,		0, &ddp_gamma },
> +	[DDP_COMPONENT_MDP_RSZ0]	= { MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
>  	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,		0, &ddp_merge },
>  	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,		1, &ddp_merge },
>  	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,		2, &ddp_merge },
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> index badb42bd4f7c..87f573fcc903 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
>  	MTK_DISP_OVLSYS_ADAPTOR,
>  	MTK_DISP_OVL_2L,
>  	MTK_DISP_OVL_ADAPTOR,
> +	MTK_DISP_MDP_RSZ,
>  	MTK_DISP_POSTMASK,
>  	MTK_DISP_PWM,
>  	MTK_DISP_RDMA,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 50f5f81a7da1..b810a197f58b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -885,6 +885,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_GAMMA, },
>  	{ .compatible = "mediatek,mt8195-disp-gamma",
>  	  .data = (void *)MTK_DISP_GAMMA, },
> +	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
> +	  .data = (void *)MTK_DISP_MDP_RSZ },
>  	{ .compatible = "mediatek,mt8195-disp-merge",
>  	  .data = (void *)MTK_DISP_MERGE },
>  	{ .compatible = "mediatek,mt2701-disp-mutex",

Re: [PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196

[CK Hu (胡俊光)]

On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> Due to the path mux design of the MT8196, the following components
> need to be added to support Picture Quality (PQ) in the main display
> path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b810a197f58b..1c97dc46ae70 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
>  
>  static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
>  	DDP_COMPONENT_DLI_ASYNC0,
> +	DDP_COMPONENT_MDP_RSZ0,
> +	DDP_COMPONENT_TDSHP0,
> +	DDP_COMPONENT_CCORR0,
> +	DDP_COMPONENT_CCORR1,
> +	DDP_COMPONENT_GAMMA0,
> +	DDP_COMPONENT_POSTMASK0,
> +	DDP_COMPONENT_DITHER0,
>  	DDP_COMPONENT_DLO_ASYNC1,
>  };
>  

Re: [PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196

[AngeloGioacchino Del Regno]

Il 17/02/25 07:06, CK Hu (胡俊光) ha scritto:
> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
>> Due to the path mux design of the MT8196, the following components
>> need to be added to support Picture Quality (PQ) in the main display
>> path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> 
>>
>> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
>> ---
>>   drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> index b810a197f58b..1c97dc46ae70 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
>>   
>>   static const unsigned int mt8196_mtk_ddp_disp0_main[] = {

If you build the display controller path with an OF graph, you don't need to
introduce any mt8196_mtk_ddp_disp0_main, at all.

Since all this work was done and upstreamed, and was done because hardcoding
the display pipeline for each board is only bloating the driver (and wrong),
just express the pipeline with a graph in the devicetree.

The driver doesn't need that array, not anymore.

Regards,
Angelo

>>   	DDP_COMPONENT_DLI_ASYNC0,
>> +	DDP_COMPONENT_MDP_RSZ0,
>> +	DDP_COMPONENT_TDSHP0,
>> +	DDP_COMPONENT_CCORR0,
>> +	DDP_COMPONENT_CCORR1,
>> +	DDP_COMPONENT_GAMMA0,
>> +	DDP_COMPONENT_POSTMASK0,
>> +	DDP_COMPONENT_DITHER0,
>>   	DDP_COMPONENT_DLO_ASYNC1,
>>   };
>>   
> 

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Sunny Shen (沈姍姍)]

On Tue, 2025-02-11 at 17:54 +0000, Conor Dooley wrote:
> On Tue, Feb 11, 2025 at 10:52:50AM +0800, Sunny Shen wrote:
> > Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> > 
> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > ---
> >  .../display/mediatek/mediatek,mdp-rsz.yaml    | 46
> > +++++++++++++++++++
> >  1 file changed, 46 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > new file mode 100644
> > index 000000000000..6642b9aa651a
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > @@ -0,0 +1,46 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml#
> 
> Filename matching compatible please

Got it
will modify the compatible to "mediatek,mt8196-mdp-rsz"

> 
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek display multimedia data path resizer
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  MediaTek display multimedia data path resizer, namely MDP-RSZ,
> > +  can do scaling up/down to the picture.
> > +
> > +properties:
> > +  compatible:
> > +    const: mediatek,mt8196-disp-mdp-rsz
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: MDP-RSZ Clock
> 
> This can just be "maxItems: 1"

OK, will modify this

> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> 
> And "disp-mdp-rsz0" isn't anything close to a generic node name.

Will modify "disp-mdp-rsz0@321a0000" to "mdp-rsz@321a0000"

> 
> > +            compatible = "mediatek,mt8196-disp-mdp-rsz";
> > +            reg = <0 0x321a0000 0 0x1000>;
> > +            clocks = <&dispsys_config_clk 101>;
> 
> Surprised there are so few properties, no ports link or anything like
> that?

Because the mt8196's path mux design, we use mdp-rsz as a bypass mode
hw.
So only set the basic properties.

> 
> > +        };
> > +    };
> > -- 
> > 2.34.1
> > 

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Sunny Shen (沈姍姍)]

On Mon, 2025-02-17 at 06:01 +0000, CK Hu (胡俊光) wrote:
> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> > 
> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > ---
> >  .../display/mediatek/mediatek,mdp-rsz.yaml    | 46
> > +++++++++++++++++++
> >  1 file changed, 46 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > new file mode 100644
> > index 000000000000..6642b9aa651a
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > rsz.yaml
> > @@ -0,0 +1,46 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!jo9-Ezn5GR8wfDCMX72zrrpxlMEYb-5w52TYinNWsQlfpiPjw5R967JIU0-6WnI5fvIU7-v0IVaRALBlW4aL$
> >  
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jo9-Ezn5GR8wfDCMX72zrrpxlMEYb-5w52TYinNWsQlfpiPjw5R967JIU0-6WnI5fvIU7-v0IVaRAIIMW8TJ$
> >  
> > +
> > +title: MediaTek display multimedia data path resizer
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  MediaTek display multimedia data path resizer, namely MDP-RSZ,
> > +  can do scaling up/down to the picture.
> > +
> > +properties:
> > +  compatible:
> > +    const: mediatek,mt8196-disp-mdp-rsz
> 
> Reference to other display mdp device compatible, use
> 
> mediatek,mt8196-mdp-rsz
> 
> Regards,
> CK

OK, will modify this


> 
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: MDP-RSZ Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> > +            compatible = "mediatek,mt8196-disp-mdp-rsz";
> > +            reg = <0 0x321a0000 0 0x1000>;
> > +            clocks = <&dispsys_config_clk 101>;
> > +        };
> > +    };
> 

Re: [PATCH 2/5] dt-bindings: display: mediatek: postmask: Modify rules for MT8196

[Sunny Shen (沈姍姍)]

On Tue, 2025-02-11 at 17:44 +0000, Conor Dooley wrote:
> On Tue, Feb 11, 2025 at 10:52:51AM +0800, Sunny Shen wrote:
> > Add a compatible string for MediaTek MT8196 SoC
> 
> $subject and $body don't match here.

OK, will modify this more precisely

> 
> > 
> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > ---
> >  .../devicetree/bindings/display/mediatek/mediatek,postmask.yaml  |
> > 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,postm
> > ask.yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,postm
> > ask.yaml
> > index fb6fe4742624..29624ac191e1 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,postm
> > ask.yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,postm
> > ask.yaml
> > @@ -27,6 +27,7 @@ properties:
> >            - enum:
> >                - mediatek,mt8186-disp-postmask
> >                - mediatek,mt8188-disp-postmask
> > +              - mediatek,mt8196-disp-postmask
> >            - const: mediatek,mt8192-disp-postmask
> >  
> >    reg:
> > -- 
> > 2.34.1
> > 

Re: [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196

[Sunny Shen (沈姍姍)]

On Mon, 2025-02-17 at 06:04 +0000, CK Hu (胡俊光) wrote:
> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > Add MDP-RSZ component support for MT8196.
> > 
> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
> >  3 files changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > index 7f09a8977965..65878d3fe8a9 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > @@ -46,6 +46,10 @@
> >  #define DSC_BYPASS				BIT(4)
> >  #define DSC_UFOE_SEL				BIT(16)
> >  
> > +#define DISP_REG_MDP_RSZ_EN			0x0000
> 
> Do you config resizer in bypass mode so you need not to enable it?

Yes, it's bypass mode
To use the hardware path for PQ,
we need set this resizer to bypass mode because the path mux design of
the MT8196

> 
> > +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> > +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> > +
> >  #define DISP_REG_OD_EN				0x0000
> >  #define DISP_REG_OD_CFG				0x0020
> >  #define OD_RELAYMODE				BIT(0)
> > @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
> >  	writel(1, priv->regs + DISP_REG_OD_EN);
> >  }
> >  
> > +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> > +			       unsigned int h, unsigned int
> > vrefresh,
> > +			       unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
> 
> Do you config resizer in bypass mode so width and height is set to
> zero?

Yes, we set resizer's width and height to 0 and use the bypass mode

> 
> Regards,
> CK
> 
> > +}
> > +
> >  static void mtk_postmask_config(struct device *dev, unsigned int
> > w,
> >  				unsigned int h, unsigned int
> > vrefresh,
> >  				unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ovlsys_adaptor = {
> >  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
> >  };
> >  
> > +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> > +	.clk_enable = mtk_ddp_clk_enable,
> > +	.clk_disable = mtk_ddp_clk_disable,
> > +	.config = mtk_mdp_rsz_config,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_postmask = {
> >  	.clk_enable = mtk_ddp_clk_enable,
> >  	.clk_disable = mtk_ddp_clk_disable,
> > @@ -454,6 +476,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >  	[MTK_DISP_DITHER] = "dither",
> >  	[MTK_DISP_DSC] = "dsc",
> >  	[MTK_DISP_GAMMA] = "gamma",
> > +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
> >  	[MTK_DISP_MERGE] = "merge",
> >  	[MTK_DISP_MUTEX] = "mutex",
> >  	[MTK_DISP_OD] = "od",
> > @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
> >  	[DDP_COMPONENT_DSI2]		= {
> > MTK_DSI,			2, &ddp_dsi },
> >  	[DDP_COMPONENT_DSI3]		= {
> > MTK_DSI,			3, &ddp_dsi },
> >  	[DDP_COMPONENT_GAMMA]		= {
> > MTK_DISP_GAMMA,		0, &ddp_gamma },
> > +	[DDP_COMPONENT_MDP_RSZ0]	= {
> > MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
> >  	[DDP_COMPONENT_MERGE0]		= {
> > MTK_DISP_MERGE,		0, &ddp_merge },
> >  	[DDP_COMPONENT_MERGE1]		= {
> > MTK_DISP_MERGE,		1, &ddp_merge },
> >  	[DDP_COMPONENT_MERGE2]		= {
> > MTK_DISP_MERGE,		2, &ddp_merge },
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > index badb42bd4f7c..87f573fcc903 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> >  	MTK_DISP_OVLSYS_ADAPTOR,
> >  	MTK_DISP_OVL_2L,
> >  	MTK_DISP_OVL_ADAPTOR,
> > +	MTK_DISP_MDP_RSZ,
> >  	MTK_DISP_POSTMASK,
> >  	MTK_DISP_PWM,
> >  	MTK_DISP_RDMA,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 50f5f81a7da1..b810a197f58b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -885,6 +885,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_GAMMA, },
> >  	{ .compatible = "mediatek,mt8195-disp-gamma",
> >  	  .data = (void *)MTK_DISP_GAMMA, },
> > +	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
> > +	  .data = (void *)MTK_DISP_MDP_RSZ },
> >  	{ .compatible = "mediatek,mt8195-disp-merge",
> >  	  .data = (void *)MTK_DISP_MERGE },
> >  	{ .compatible = "mediatek,mt2701-disp-mutex",
> 

Re: [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196

[CK Hu (胡俊光)]

On Sun, 2025-02-23 at 17:52 +0000, Sunny Shen (沈姍姍) wrote:
> On Mon, 2025-02-17 at 06:04 +0000, CK Hu (胡俊光) wrote:
> > On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > > Add MDP-RSZ component support for MT8196.
> > > 
> > > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24
> > > ++++++++++++++++++++++++
> > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
> > >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
> > >  3 files changed, 27 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > index 7f09a8977965..65878d3fe8a9 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > @@ -46,6 +46,10 @@
> > >  #define DSC_BYPASS				BIT(4)
> > >  #define DSC_UFOE_SEL				BIT(16)
> > >  
> > > +#define DISP_REG_MDP_RSZ_EN			0x0000
> > 
> > Do you config resizer in bypass mode so you need not to enable it?
> 
> Yes, it's bypass mode
> To use the hardware path for PQ,
> we need set this resizer to bypass mode because the path mux design of
> the MT8196
> 
> > 
> > > +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> > > +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> > > +
> > >  #define DISP_REG_OD_EN				0x0000
> > >  #define DISP_REG_OD_CFG				0x0020
> > >  #define OD_RELAYMODE				BIT(0)
> > > @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
> > >  	writel(1, priv->regs + DISP_REG_OD_EN);
> > >  }
> > >  
> > > +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> > > +			       unsigned int h, unsigned int
> > > vrefresh,
> > > +			       unsigned int bpc, struct cmdq_pkt
> > > *cmdq_pkt)
> > > +{
> > > +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > +
> > > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > > +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> > > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > > +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
> > 
> > Do you config resizer in bypass mode so width and height is set to
> > zero?
> 
> Yes, we set resizer's width and height to 0 and use the bypass mode

Add comment for this so others would know why not enable it and why set width/height to zero.

Regards,
CK

> 
> > 
> > Regards,
> > CK
> > 
> > > +}
> > > +
> > >  static void mtk_postmask_config(struct device *dev, unsigned int
> > > w,
> > >  				unsigned int h, unsigned int
> > > vrefresh,
> > >  				unsigned int bpc, struct cmdq_pkt
> > > *cmdq_pkt)
> > > @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs
> > > ddp_ovlsys_adaptor = {
> > >  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
> > >  };
> > >  
> > > +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> > > +	.clk_enable = mtk_ddp_clk_enable,
> > > +	.clk_disable = mtk_ddp_clk_disable,
> > > +	.config = mtk_mdp_rsz_config,
> > > +};
> > > +
> > >  static const struct mtk_ddp_comp_funcs ddp_postmask = {
> > >  	.clk_enable = mtk_ddp_clk_enable,
> > >  	.clk_disable = mtk_ddp_clk_disable,
> > > @@ -454,6 +476,7 @@ static const char * const
> > > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > >  	[MTK_DISP_DITHER] = "dither",
> > >  	[MTK_DISP_DSC] = "dsc",
> > >  	[MTK_DISP_GAMMA] = "gamma",
> > > +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
> > >  	[MTK_DISP_MERGE] = "merge",
> > >  	[MTK_DISP_MUTEX] = "mutex",
> > >  	[MTK_DISP_OD] = "od",
> > > @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match
> > > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
> > >  	[DDP_COMPONENT_DSI2]		= {
> > > MTK_DSI,			2, &ddp_dsi },
> > >  	[DDP_COMPONENT_DSI3]		= {
> > > MTK_DSI,			3, &ddp_dsi },
> > >  	[DDP_COMPONENT_GAMMA]		= {
> > > MTK_DISP_GAMMA,		0, &ddp_gamma },
> > > +	[DDP_COMPONENT_MDP_RSZ0]	= {
> > > MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
> > >  	[DDP_COMPONENT_MERGE0]		= {
> > > MTK_DISP_MERGE,		0, &ddp_merge },
> > >  	[DDP_COMPONENT_MERGE1]		= {
> > > MTK_DISP_MERGE,		1, &ddp_merge },
> > >  	[DDP_COMPONENT_MERGE2]		= {
> > > MTK_DISP_MERGE,		2, &ddp_merge },
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > index badb42bd4f7c..87f573fcc903 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> > >  	MTK_DISP_OVLSYS_ADAPTOR,
> > >  	MTK_DISP_OVL_2L,
> > >  	MTK_DISP_OVL_ADAPTOR,
> > > +	MTK_DISP_MDP_RSZ,
> > >  	MTK_DISP_POSTMASK,
> > >  	MTK_DISP_PWM,
> > >  	MTK_DISP_RDMA,
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > index 50f5f81a7da1..b810a197f58b 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > @@ -885,6 +885,8 @@ static const struct of_device_id
> > > mtk_ddp_comp_dt_ids[] = {
> > >  	  .data = (void *)MTK_DISP_GAMMA, },
> > >  	{ .compatible = "mediatek,mt8195-disp-gamma",
> > >  	  .data = (void *)MTK_DISP_GAMMA, },
> > > +	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
> > > +	  .data = (void *)MTK_DISP_MDP_RSZ },
> > >  	{ .compatible = "mediatek,mt8195-disp-merge",
> > >  	  .data = (void *)MTK_DISP_MERGE },
> > >  	{ .compatible = "mediatek,mt2701-disp-mutex",
> > 
> 

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 706 bytes --]

On Sun, Feb 23, 2025 at 05:49:45PM +0000, Sunny Shen (沈姍姍) wrote:
> On Tue, 2025-02-11 at 17:54 +0000, Conor Dooley wrote:
> > On Tue, Feb 11, 2025 at 10:52:50AM +0800, Sunny Shen wrote:
> > > Add MDP-RSZ hardware description for MediaTek MT8196 SoC

> > > +examples:
> > > +  - |
> > > +    soc {
> > > +        #address-cells = <2>;
> > > +        #size-cells = <2>;
> > > +
> > > +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> > 
> > And "disp-mdp-rsz0" isn't anything close to a generic node name.
> 
> Will modify "disp-mdp-rsz0@321a0000" to "mdp-rsz@321a0000"

I don't think that's an improvement. Hint: full words would be a good
place to start

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Sunny Shen (沈姍姍)]

On Mon, 2025-02-24 at 19:01 +0000, Conor Dooley wrote:
> On Sun, Feb 23, 2025 at 05:49:45PM +0000, Sunny Shen (沈姍姍) wrote:
> > On Tue, 2025-02-11 at 17:54 +0000, Conor Dooley wrote:
> > > On Tue, Feb 11, 2025 at 10:52:50AM +0800, Sunny Shen wrote:
> > > > Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> 
> > > > +examples:
> > > > +  - |
> > > > +    soc {
> > > > +        #address-cells = <2>;
> > > > +        #size-cells = <2>;
> > > > +
> > > > +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> > > 
> > > And "disp-mdp-rsz0" isn't anything close to a generic node name.
> > 
> > Will modify "disp-mdp-rsz0@321a0000" to "mdp-rsz@321a0000"
> 
> I don't think that's an improvement. Hint: full words would be a good
> place to start

 
Hi Conor,

About full words, 
Do you mean words like this? 
multimedia-display-path-resizer?
or mdp-resizer?

We found that "mdp-rsz" this kind of word is used at
https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/mediatek/mt8183.dtsi

I'm not sure what will be better.
Can you provide more detailed suggestion about this naming?

Thank you


BR,
Sunny Shen

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1365 bytes --]

On Tue, Mar 18, 2025 at 03:14:07AM +0000, Sunny Shen (沈姍姍) wrote:
> On Mon, 2025-02-24 at 19:01 +0000, Conor Dooley wrote:
> > On Sun, Feb 23, 2025 at 05:49:45PM +0000, Sunny Shen (沈姍姍) wrote:
> > > On Tue, 2025-02-11 at 17:54 +0000, Conor Dooley wrote:
> > > > On Tue, Feb 11, 2025 at 10:52:50AM +0800, Sunny Shen wrote:
> > > > > Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> > 
> > > > > +examples:
> > > > > +  - |
> > > > > +    soc {
> > > > > +        #address-cells = <2>;
> > > > > +        #size-cells = <2>;
> > > > > +
> > > > > +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> > > > 
> > > > And "disp-mdp-rsz0" isn't anything close to a generic node name.
> > > 
> > > Will modify "disp-mdp-rsz0@321a0000" to "mdp-rsz@321a0000"
> > 
> > I don't think that's an improvement. Hint: full words would be a good
> > place to start
> 
>  
> Hi Conor,
> 
> About full words, 
> Do you mean words like this? 
> multimedia-display-path-resizer?
> or mdp-resizer?

These are both improvements on what you've got right now.

> We found that "mdp-rsz" this kind of word is used at
> https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> 
> I'm not sure what will be better.
> Can you provide more detailed suggestion about this naming?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196

[Sunny Shen (沈姍姍)]

On Wed, 2025-03-19 at 20:00 +0000, Conor Dooley wrote:
> On Tue, Mar 18, 2025 at 03:14:07AM +0000, Sunny Shen (沈姍姍) wrote:
> > On Mon, 2025-02-24 at 19:01 +0000, Conor Dooley wrote:
> > > On Sun, Feb 23, 2025 at 05:49:45PM +0000, Sunny Shen (沈姍姍) wrote:
> > > > On Tue, 2025-02-11 at 17:54 +0000, Conor Dooley wrote:
> > > > > On Tue, Feb 11, 2025 at 10:52:50AM +0800, Sunny Shen wrote:
> > > > > > Add MDP-RSZ hardware description for MediaTek MT8196 SoC
> > > 
> > > > > > +examples:
> > > > > > +  - |
> > > > > > +    soc {
> > > > > > +        #address-cells = <2>;
> > > > > > +        #size-cells = <2>;
> > > > > > +
> > > > > > +        disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> > > > > 
> > > > > And "disp-mdp-rsz0" isn't anything close to a generic node
> > > > > name.
> > > > 
> > > > Will modify "disp-mdp-rsz0@321a0000" to "mdp-rsz@321a0000"
> > > 
> > > I don't think that's an improvement. Hint: full words would be a
> > > good
> > > place to start
> > 
> >  
> > Hi Conor,
> > 
> > About full words, 
> > Do you mean words like this? 
> > multimedia-display-path-resizer?
> > or mdp-resizer?
> 
> These are both improvements on what you've got right now.

Okay~
I'll use mdp-resizer for this


> 
> > We found that "mdp-rsz" this kind of word is used at
> > https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > 
> > I'm not sure what will be better.
> > Can you provide more detailed suggestion about this naming?

Re: [PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196

[Sunny Shen (沈姍姍)]

On Mon, 2025-02-17 at 15:25 +0100, AngeloGioacchino Del Regno wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 17/02/25 07:06, CK Hu (胡俊光) ha scritto:
> > On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > > Due to the path mux design of the MT8196, the following
> > > components
> > > need to be added to support Picture Quality (PQ) in the main
> > > display
> > > path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0,
> > > TDSHP0.
> > 
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > 
> > > 
> > > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > > ---
> > >   drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
> > >   1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > index b810a197f58b..1c97dc46ae70 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > @@ -242,6 +242,13 @@ static const unsigned int
> > > mt8196_mtk_ddp_ovl0_main[] = {
> > > 
> > >   static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
> 
> If you build the display controller path with an OF graph, you don't
> need to
> introduce any mt8196_mtk_ddp_disp0_main, at all.
> 
> Since all this work was done and upstreamed, and was done because
> hardcoding
> the display pipeline for each board is only bloating the driver (and
> wrong),
> just express the pipeline with a graph in the devicetree.
> 
> The driver doesn't need that array, not anymore.
> 
> Regards,
> Angelo

Hi Angelo,

Thank you for the review
 
We are still investigating the method of using OF graph.
I can find a patch of add controllor graph here
(https://patchwork.kernel.org/project/linux-mediatek/patch/20250220110948.45596-2-angelogioacchino.delregno@collabora.com/
)
May I ask that is there any example of driver config display path by OF
graph?
 
And since the path control is not the main topic of PQ support.
Should we discard the change of this file
and modify the patch added path of mt8196?
(https://patchwork.kernel.org/project/linux-mediatek/patch/20250321093435.94835-16-paul-pl.chen@mediatek.com/
)
Or add a new patch series?

Regards,
Sunny

> 
> > >      DDP_COMPONENT_DLI_ASYNC0,
> > > +    DDP_COMPONENT_MDP_RSZ0,
> > > +    DDP_COMPONENT_TDSHP0,
> > > +    DDP_COMPONENT_CCORR0,
> > > +    DDP_COMPONENT_CCORR1,
> > > +    DDP_COMPONENT_GAMMA0,
> > > +    DDP_COMPONENT_POSTMASK0,
> > > +    DDP_COMPONENT_DITHER0,
> > >      DDP_COMPONENT_DLO_ASYNC1,
> > >   };
> > > 
> > 
> 
> 
>