Re: [PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845

[Taniya Das <tdas@codeaurora.org>]

On 9/6/2018 7:21 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-09-05 11:26:10)
>> On 8/28/2018 2:41 AM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2018-08-03 05:21:14)
>>>> diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
>>>> new file mode 100644
>>>> index 0000000..6f387f9
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/lpasscc-sdm845.c
>>> [...]
>>>> +
>>>> +/* CLK_OFF would not toggle until LPASS is not out of reset */
>>>
>>> Can we change the branch ops to check for out of reset or not? Do the
>>> clks even work when LPASS isn't out of reset? Why would the clk APIs
>>> even be called on here if it hadn't taken LPASS out of reset?
>>>
>>
>> The branches need to be turned ON before the LPASS is out of reset.
>> But we would not be able to check the CLK_ENABLE bit.
> 
> Ok. Are the branches actually outputting any clk frequency when LPASS is
> in reset? It sounds like the hardware is broken and we can't ever check
> the halt bits?
> 
Yes, they would output when the reset is pulled for LPASS. These are as 
per the steps to be followed to bring the LPASS out of reset.

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