Re: [PATCH 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

["Nazle Asmade, Muhammad Nazim Amirul" <muhammad.nazim.amirul.nazle.asmade@altera.com>]

On 15/5/2026 7:43 am, Dinh Nguyen wrote:
> 
> 
> On 5/14/26 06:41, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>
>> The SMMU is enabled and transactions going through it are cache
>> coherent. Add the dma-coherent property to the XGMAC nodes to prevent
>> redundant cache flush/invalidate operations and potential stale data
>> issues.
>>
>> Signed-off-by: Nazim Amirul 
>> <muhammad.nazim.amirul.nazle.asmade@altera.com>
>> ---
>>   arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
>>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 1 +
>>   5 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/ 
>> arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>> index 25e17df0cbdb..2061d301126e 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
>> @@ -52,6 +52,7 @@ &gmac2 {
>>       phy-mode = "rgmii-id";
>>       phy-handle = <&emac2_phy0>;
>>       max-frame-size = <9000>;
>> +    dma-coherent;
> This property should be in placed in the Agilex5 dtsi file.
> 
> Thanks,
> Dinh
All the changes had been reflected in v2. Thanks Dinh!

https://lore.kernel.org/all/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com/

https://lore.kernel.org/all/20260515080014.6260-2-muhammad.nazim.amirul.nazle.asmade@altera.com/

https://lore.kernel.org/all/20260515080014.6260-3-muhammad.nazim.amirul.nazle.asmade@altera.com/

BR,
Nazim