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From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	"Conor Dooley" <conor+dt@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v5 2/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Wed, 28 Jun 2023 14:44:10 +0800	[thread overview]
Message-ID: <a83c98ae-2f6c-00c4-5d05-fc304718e05a@starfivetech.com> (raw)
In-Reply-To: <7e2d6bfe-5687-97c5-778b-c02e9c0894af@linaro.org>

On 2023/6/14 2:31, Krzysztof Kozlowski wrote:
> On 13/06/2023 14:58, Xingyu Wu wrote:
>> From: William Qiu <william.qiu@starfivetech.com>
>> 
>> Add documentation to describe StarFive System Controller Registers.
>> 
>> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 62 +++++++++++++++++++
>>  MAINTAINERS                                   |  7 +++
>>  2 files changed, 69 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..a81190f8a54d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -0,0 +1,62 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> +  - William Qiu <william.qiu@starfivetech.com>
>> +
>> +description: |
>> +  The StarFive JH7110 SoC system controller provides register information such
>> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> +  compatible:
>> +    oneOf:
>> +      - items:
>> +          - const: starfive,jh7110-sys-syscon
>> +          - const: syscon
>> +          - const: simple-mfd
>> +      - items:
>> +          - enum:
>> +              - starfive,jh7110-aon-syscon
>> +              - starfive,jh7110-stg-syscon
>> +          - const: syscon
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clock-controller:
>> +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> +    type: object
>> +
>> +  "#power-domain-cells":
>> +    const: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: starfive,jh7110-aon-syscon
>> +    then:
>> +      required:
>> +        - "#power-domain-cells"
> 
> Where did you implement the results of the discussion that only some
> devices can have power and clock controller?
> 
> According to your code all of above - sys, aon and stg - have clock and
> power controllers. If not, then the code is not correct, so please do
> not respond with what is where (like you did last time) but actually
> implement what you say.
> 

Hi Krzysztof, I need to modify the code to implement it.
If I drop the 'clock-controller' and '"#power-domain-cells"' in properites, and change to this:

--- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -29,28 +29,33 @@ properties:
   reg:
     maxItems: 1
 
-  clock-controller:
-    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
-    type: object
-
-  "#power-domain-cells":
-    const: 1
-
 required:
   - compatible
   - reg
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jh7110-sys-syscon
+    then:
+      properties:
+        clock-controller:
+          $ref: /schemas/clock/starfive,jh7110-pll.yaml#
+          type: object
+
   - if:
       properties:
         compatible:
           contains:
             const: starfive,jh7110-aon-syscon
     then:
-      required:
-        - "#power-domain-cells"
+      properties:
+        "#power-domain-cells":
+          const: 1
 
-additionalProperties: false
+additionalProperties: true


Would it be better to show that sys-syscon only has clock-controller and aon-syscon is power controller?

Best regards,
Xingyu Wu


  reply	other threads:[~2023-06-28  8:57 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-13 12:58 [PATCH v5 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-06-13 19:06   ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-06-13 18:31   ` Krzysztof Kozlowski
2023-06-28  6:44     ` Xingyu Wu [this message]
2023-06-28 17:34       ` Conor Dooley
2023-06-29  6:42         ` Xingyu Wu
2023-06-29  9:01           ` Conor Dooley
2023-06-13 18:32   ` Krzysztof Kozlowski
2023-06-13 12:58 ` [PATCH v5 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-06-13 18:34   ` Krzysztof Kozlowski
2023-06-13 19:17     ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-06-13 19:58   ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 7/7] riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG node Xingyu Wu
2023-06-13 19:55   ` Conor Dooley

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