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([2001:818:ea8e:7f00:2575:914:eedd:620e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38378csm12453754f8f.25.2025.01.13.08.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 08:05:28 -0800 (PST) Message-ID: Subject: Re: [PATCH v3 4/9] iio: dac: adi-axi-dac: add bus mode setup From: Nuno =?ISO-8859-1?Q?S=E1?= To: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno Sa Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 13 Jan 2025 16:05:26 +0000 In-Reply-To: <20250110-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v3-4-ab42aef0d840@baylibre.com> References: <20250110-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v3-0-ab42aef0d840@baylibre.com> <20250110-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v3-4-ab42aef0d840@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2025-01-10 at 11:24 +0100, Angelo Dureghello wrote: > From: Angelo Dureghello >=20 > The ad354xr requires DSPI mode (2 data lanes) to work in buffering > mode, so backend needs to allow a mode selection between: > =C2=A0=C2=A0=C2=A0 SPI=C2=A0 (entire ad35xxr family), > =C2=A0=C2=A0=C2=A0 DSPI (ad354xr), > =C2=A0=C2=A0=C2=A0 QSPI (ad355xr). >=20 I guess this could be misleading people to think this is being handled by t= he backend framework when it's not. I would rephrase things a bit in here. > About removal of AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER, according to > the HDL history the flag has never been used. So looks like the driver > was including it by mistake or in anticipation for something that was > never implemented on HDL side. >=20 > Current HDL updated documentation confirm it is actually not in use > anymore and replaced by the IO_MODE bits. >=20 > Signed-off-by: Angelo Dureghello > --- With the improved change and the inline note: Reviewed-by: Nuno Sa > =C2=A0drivers/iio/dac/ad3552r-hs.h=C2=A0 |=C2=A0 8 ++++++++ > =C2=A0drivers/iio/dac/adi-axi-dac.c | 22 +++++++++++++++++++++- > =C2=A02 files changed, 29 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/iio/dac/ad3552r-hs.h b/drivers/iio/dac/ad3552r-hs.h > index 724261d38dea..4a9e35234124 100644 > --- a/drivers/iio/dac/ad3552r-hs.h > +++ b/drivers/iio/dac/ad3552r-hs.h > @@ -8,11 +8,19 @@ > =C2=A0 > =C2=A0struct iio_backend; > =C2=A0 > +enum ad3552r_io_mode { > + AD3552R_IO_MODE_SPI, > + AD3552R_IO_MODE_DSPI, > + AD3552R_IO_MODE_QSPI, > +}; > + > =C2=A0struct ad3552r_hs_platform_data { > =C2=A0 int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val, > =C2=A0 =C2=A0=C2=A0=C2=A0 size_t data_size); > =C2=A0 int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0 size_t data_size); > + int (*bus_set_io_mode)(struct iio_backend *back, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 enum ad3552r_io_mode mode); > =C2=A0 u32 bus_sample_data_clock_hz; > =C2=A0}; > =C2=A0 > diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.= c > index ac871deb8063..bcaf365feef4 100644 > --- a/drivers/iio/dac/adi-axi-dac.c > +++ b/drivers/iio/dac/adi-axi-dac.c > @@ -64,7 +64,7 @@ > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_UI_STATUS_IF_BUSY BIT(4) > =C2=A0#define AXI_DAC_CUSTOM_CTRL_REG 0x008C > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24) > -#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER BIT(2) > +#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2) > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_STREAM BIT(1) > =C2=A0#define=C2=A0=C2=A0 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0) > =C2=A0 > @@ -722,6 +722,25 @@ static int axi_dac_bus_reg_read(struct iio_backend *= back, > u32 reg, u32 *val, > =C2=A0 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); > =C2=A0} > =C2=A0 > +static int axi_dac_bus_set_io_mode(struct iio_backend *back, > + =C2=A0=C2=A0 enum ad3552r_io_mode mode) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + int ival, ret; > + No harm in doing some validation on 'mode'. - Nuno S=C3=A1 > + guard(mutex)(&st->lock); > + > + ret =3D regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, > + AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, > + FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode)); > + if (ret) > + return ret; > + > + return regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, > ival, > + FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) =3D=3D 0, 10, > + 100 * KILO); > +} > + > =C2=A0static void axi_dac_child_remove(void *data) > =C2=A0{ > =C2=A0 platform_device_unregister(data); > @@ -733,6 +752,7 @@ static int axi_dac_create_platform_device(struct > axi_dac_state *st, > =C2=A0 struct ad3552r_hs_platform_data pdata =3D { > =C2=A0 .bus_reg_read =3D axi_dac_bus_reg_read, > =C2=A0 .bus_reg_write =3D axi_dac_bus_reg_write, > + .bus_set_io_mode =3D axi_dac_bus_set_io_mode, > =C2=A0 .bus_sample_data_clock_hz =3D st->dac_clk_rate, > =C2=A0 }; > =C2=A0 struct platform_device_info pi =3D { >=20