From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A5D341ACB; Thu, 18 Dec 2025 10:18:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766053084; cv=none; b=lGHyt6B1o6NcGpOKjxAXbGqw5SAN2ZJrTO3nyv6dKpSoPOLkO2fQRquVLWbqJgiag8R8oLnR4TtSVdHk/FKu04Sw56LyqKhJXtyx19iQWCxREfm0SRyeP+9thDkSwOUFMUVZEi6IqeQUoTJLdo9zmn7zXVJCjlYCTKBMlm0dtCU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766053084; c=relaxed/simple; bh=bxrqB9iSN80kbhnaAWO3v0ub+BG8cV05W//Bp9WiPh0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=YvVUo0k0sFDTFbR2X2kIYHoNqlRkrGKWlRm+jR/Xofhhb6yEwiHydO1WmGveZ1Xbi5OgByj9VCBi8/GKuBbzysP9pzIA3C5B5QRFx0CjWF6pSPpOInKlPSPcwYla1A6viF5yq6nX/+ZVlSS9+6Eo1kXqMRu0LkRI+bRAytry/QQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jc1gq3br; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jc1gq3br" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15B25C4CEFB; Thu, 18 Dec 2025 10:17:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766053082; bh=bxrqB9iSN80kbhnaAWO3v0ub+BG8cV05W//Bp9WiPh0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=jc1gq3brsBpzaQ7E4X3Ecd7VjX24JIW1WvIk1E0wQV2wYhF8nyJVte9F2SBYWDQJh A2ofSAaYE6Gf5VTYW0L60wcEg/z0f0RgNHKMpoN77FcZXFKLLlv2ql42kYbDd6fFSV Siz6bNPNjoIdKSTbms8QjpH6pVcyVhN7q5S1OpQt8aw1SQzVoky+Qwu23w/WWgq9DU 72sSy6AYocZEJpDZEYG5ehzoA3oUiTPG/MFdaCirlhU/+ZPqz93EM2/KhR56ir6x4Z OhvUKtWu4N9LYealnEyH+nWEjvXQaBkWRp7GrBUgWXIY6dzHwIbLs95Kujo85Q3B+p fr5CxSedtIsmg== Message-ID: Date: Thu, 18 Dec 2025 11:17:57 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU To: Jie Gan , Rob Herring Cc: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20251211-enable-byte-cntr-for-ctcu-v8-0-3e12ff313191@oss.qualcomm.com> <20251211-enable-byte-cntr-for-ctcu-v8-5-3e12ff313191@oss.qualcomm.com> <20251211133723.GA859302-robh@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 12/12/2025 02:12, Jie Gan wrote: > > > On 12/11/2025 9:37 PM, Rob Herring wrote: >> On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote: >>> Add an interrupt property to CTCU device. The interrupt will be triggered >>> when the data size in the ETR buffer exceeds the threshold of the >>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register >>> of CTCU device will enable the interrupt. >>> >>> Acked-by: Krzysztof Kozlowski >>> Reviewed-by: Mike Leach >>> Signed-off-by: Jie Gan >>> --- >>> .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ >>> 1 file changed, 17 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >>> index c969c16c21ef..90f88cc6cd3e 100644 >>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >>> @@ -39,6 +39,16 @@ properties: >>> items: >>> - const: apb >>> >>> + interrupts: >>> + items: >>> + - description: Byte cntr interrupt for the first etr device >>> + - description: Byte cntr interrupt for the second etr device >>> + >>> + interrupt-names: >>> + items: >>> + - const: etrirq0 >>> + - const: etrirq1 >> >> Names are kind of pointless when it is just foo. > > Hi Rob, > > I was naming them as etr0/etr1. Are these names acceptable? Obviously irq is redundant, but how does etr0 solves the problem of calling it foo0? I don't think you really read Rob's comment. > The interrupts are assigned exclusively to a specific ETR device. > > But Suzuki is concerned that this might cause confusion because the ETR > device is named randomly in the driver. Suzuki suggested using ‘port-0’ > and ‘port-1’ and would also like to hear your feedback on these names. There is no confusion here. Writing bindings luckily clarifies this what the indices in the array mean. > > Usually, the probe sequence follows the order of the addresses. In our > specification, ‘ETR0’ is always probed before ‘ETR1’ because its address > is lower. How is this even relevant? You are answering to something completely different, so I don't think you really tried to understand review. Best regards, Krzysztof