From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-185.mta0.migadu.com (out-185.mta0.migadu.com [91.218.175.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3653020311 for ; Thu, 29 Jan 2026 17:46:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.185 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769708804; cv=none; b=hP3ojo9DOHFYuOFXCThly5eZedOrlDCJYdF+Wk1qPR+Rv5CwiMWzHdagFPbaSMUf319ROLlKFn/uUolcgIL0pBDuc08iHd4loGuHR5N2khseGFKYCOja8FH6sUZJPf6CA3XJb0n7PPxUF6Ol2bkSUThMrJNU0HJ11SdsU4i6Vs4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769708804; c=relaxed/simple; bh=j+If/SlmCSsO1CTWiFJJ53NTq+WpBRYaTVktnI1rx/I=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=IvseOkluSqgHh1x9+///lJ8ThGsnxZnyKZTjsScRWrHPyS2+LNFw8XRUgxN38t8fbf+UacBUXzbesD5Yt2TFK0ym5oJeu3ky7/0S0NrhGLXeNI2JG8zGK3IS306pMz5AU1bP+LMcxfXTkaZbYUgvM/jGASH10CWDeASG4kt6QMM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=sY+tz50A; arc=none smtp.client-ip=91.218.175.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="sY+tz50A" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1769708791; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sbQkO/aU6GO1ByLXLbgZaMgMyf+e1d/FazyAtfU3Usc=; b=sY+tz50AYFXBsC6bljckZOdSlmfyEXAcftS8CKgQCNTOjImPluZCAXtLfgcvmvE4s1lvEM +sN8/m4q5L5ohdcFHV5t5g0m/xQ3gvgfXinC3WU3hRdmh6ZyskdGACWzD94JEcOFOPjjnL VyfKUFzpi02PxRmAbM2lG1zaUE+TMiU= Date: Thu, 29 Jan 2026 12:46:27 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH 2/2] ASoC: xilinx: xlnx_i2s: Discover parameters from registers To: Mark Brown Cc: Vincenzo Frascino , Liam Girdwood , linux-sound@vger.kernel.org, Jaroslav Kysela , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michal Simek , Takashi Iwai References: <20260129172315.3871602-1-sean.anderson@linux.dev> <20260129172315.3871602-3-sean.anderson@linux.dev> <700e4e67-a2ed-4b37-a00b-303bbc5ee6cd@sirena.org.uk> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson In-Reply-To: <700e4e67-a2ed-4b37-a00b-303bbc5ee6cd@sirena.org.uk> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 1/29/26 12:27, Mark Brown wrote: > On Thu, Jan 29, 2026 at 12:23:15PM -0500, Sean Anderson wrote: > >> - ret = of_property_read_u32(node, "xlnx,num-channels", &drv_data->channels); > >> - ret = of_property_read_u32(node, "xlnx,dwidth", &drv_data->data_width); > > Given that the properties already exist it seems wise to continue to > parse them if available and prefer them over what we read from the > hardware, it would not shock me to discover that hardware exists where > the registers are inaccurate or need overriding due to bugs. I would be surprised if such hardware exists. These properties are automatically generated by Xilinx's tools based on the HDL core's properties. This has a few consequences: - They always exactly match the hardware unless someone has gone in and modified them. I think this is unlikely in this case because they directly reflect parameters that should not need to be adjusted. - Driver authors tend to use them even when there are hardware registers available with the same information, as Xilinx has not always been consistent in adding such registers. I am not aware of any errata regarding incorrect generation of properties for this device or cases where the number of channels or bit depth was incorrect. --Sean