From: Ingo Molnar <mingo@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: "Arnd Bergmann" <arnd@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
"Juergen Gross" <jgross@suse.com>,
"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
"Alexander Usyskin" <alexander.usyskin@intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Mateusz Jończyk" <mat.jonczyk@o2.pl>,
"Mike Rapoport" <rppt@kernel.org>,
"Ard Biesheuvel" <ardb@kernel.org>,
"Peter Zijlstra" <peterz@infradead.org>,
linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org,
"Linus Torvalds" <torvalds@linux-foundation.org>
Subject: Re: [PATCH] [RFC] x86/cpu: rework instruction set selection
Date: Sat, 26 Apr 2025 21:09:50 +0200 [thread overview]
Message-ID: <aA0vft1cPuvzdZvJ@gmail.com> (raw)
In-Reply-To: <d2b0e71c-e79b-40d6-8693-3202cd894d66@app.fastmail.com>
* Arnd Bergmann <arnd@arndb.de> wrote:
> CMOV is missing not just on old Socket 5/7 CPUs (Pentium MMX, AMD K6,
> Cyrix MII) but also newer embedded Via C3, Geode GX and
> Vortex86DX/MX/EX/DX2. The replacement Nehemiah (2003), GeodeLX (2005)
> and Vortex86DX3/EX2 (2015!) have CMOV, but the old ones were sold
> alongside them for years, and some of the 586-class Vortex86 products
> are still commercially available.
Very few (if any) of the commercially available products will run
modern 6.16+ kernels, right?
Note that the real danger the 32-bit x86 kernel is going to be facing
in 2-5 years is total removal due to lack of development interest, but
I think we can support 686+ reasonably far into the future, and can
keep it tested reasonably - while covering like 99%+ of the currently
available 32-bit-only x86 products on the market. The fewer variants,
the better.
Thanks,
Ingo
next prev parent reply other threads:[~2025-04-26 19:09 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-25 14:15 [PATCH] [RFC] x86/cpu: rework instruction set selection Arnd Bergmann
2025-04-25 15:34 ` H. Peter Anvin
2025-04-25 16:13 ` Arnd Bergmann
2025-04-25 20:15 ` H. Peter Anvin
2025-04-26 9:08 ` Ingo Molnar
2025-04-26 13:17 ` H. Peter Anvin
2025-04-26 18:55 ` Ingo Molnar
2025-04-27 0:35 ` H. Peter Anvin
2025-04-26 18:58 ` Arnd Bergmann
2025-04-26 19:09 ` Ingo Molnar [this message]
2025-04-27 13:24 ` Arnd Bergmann
2025-04-27 21:17 ` H. Peter Anvin
2025-04-26 19:24 ` Linus Torvalds
2025-04-26 19:55 ` Linus Torvalds
2025-04-26 23:47 ` H. Peter Anvin
2025-04-27 10:18 ` Ingo Molnar
2025-04-27 0:02 ` H. Peter Anvin
2025-04-27 19:17 ` Andrew Cooper
2025-04-27 19:34 ` Linus Torvalds
2025-04-27 21:14 ` H. Peter Anvin
2025-04-28 6:58 ` [PATCH] bitops/32: Convert variable_ffs() and fls() zero-case handling to C Ingo Molnar
2025-04-28 7:05 ` Ingo Molnar
2025-04-28 7:14 ` Ingo Molnar
2025-04-28 12:30 ` Arnd Bergmann
2025-04-28 13:41 ` H. Peter Anvin
2025-04-28 16:23 ` Linus Torvalds
2025-04-29 10:08 ` Ingo Molnar
2025-04-29 14:32 ` H. Peter Anvin
2025-04-28 16:14 ` Linus Torvalds
2025-04-28 21:38 ` H. Peter Anvin
2025-04-29 0:12 ` Andrew Cooper
2025-04-29 2:00 ` H. Peter Anvin
2025-04-29 2:22 ` Linus Torvalds
2025-04-29 2:25 ` Andrew Cooper
2025-04-29 3:13 ` H. Peter Anvin
2025-04-29 14:38 ` Andrew Cooper
2025-04-29 18:05 ` Linus Torvalds
2025-04-29 19:13 ` Andrew Cooper
2025-04-29 20:12 ` Linus Torvalds
2025-04-29 21:23 ` H. Peter Anvin
2025-04-29 21:53 ` Linus Torvalds
2025-04-29 21:59 ` Andrew Cooper
2025-04-29 22:04 ` Linus Torvalds
2025-04-29 22:10 ` H. Peter Anvin
2025-04-29 22:22 ` Andrew Cooper
2025-04-29 22:34 ` Linus Torvalds
2025-04-27 9:50 ` [PATCH] [RFC] x86/cpu: rework instruction set selection Ingo Molnar
2025-04-30 21:54 ` David Laight
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