[PATCH] PCI: dw-rockchip: Configure max payload size on host init

Hans Zhang
2025-04-16T15:20:29Z

The RK3588's PCIe controller defaults to a 128-byte max payload size,
but its hardware capability actually supports 256 bytes. This results
in suboptimal performance with devices that support larger payloads.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index c624b7ebd118..5bbb536a2576 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -477,6 +477,22 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
return IRQ_HANDLED;
}

+static void rockchip_pcie_set_max_payload(struct rockchip_pcie *rockchip)
+{
+ struct dw_pcie *pci = &rockchip->pci;
+ u32 dev_cap, dev_ctrl;
+ u16 offset;
+
+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ dev_cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCAP);
+ dev_cap &= PCI_EXP_DEVCAP_PAYLOAD;
+
+ dev_ctrl = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
+ dev_ctrl &= ~PCI_EXP_DEVCTL_PAYLOAD;
+ dev_ctrl |= dev_cap << 5;
+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, dev_ctrl);
+}
+
static int rockchip_pcie_configure_rc(struct platform_device *pdev,
struct rockchip_pcie *rockchip)
{
@@ -511,6 +527,8 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev,
pp->ops = &rockchip_pcie_host_ops;
pp->use_linkup_irq = true;

+ rockchip_pcie_set_max_payload(rockchip);
+
ret = dw_pcie_host_init(pp);
if (ret) {
dev_err(dev, "failed to initialize host\n");

base-commit: a24588245776dafc227243a01bfbeb8a59bafba9
--
2.25.1