Re: [PATCH v3 10/10] pinctrl: Add pin controller driver for AAEON UP boards

Linus Walleij
2025-04-17T07:57:15Z

On Wed, Apr 16, 2025 at 4:08 PM Thomas Richard
<thomas.richard@bootlin.com> wrote:

> This enables the pin control support of the onboard FPGA on AAEON UP
> boards.
>
> This FPGA acts as a level shifter between the Intel SoC pins and the pin
> header, and also as a mux or switch.
>
> +---------+ +--------------+ +---+
> | | | | |
> | PWM0 | \ | | H |
> |----------|------ \-----|-------------| E |
> | I2C0_SDA | | | A |
> Intel SoC |----------|------\ | | D |
> | GPIO0 | \------|-------------| E |
> |----------|------ | | R |
> | | FPGA | | |
> ----------+ +--------------+ +---+
>
> For most of the pins, the FPGA opens/closes a switch to enable/disable
> the access to the SoC pin from a pin header.
> Each switch, has a direction flag that is set depending the status of the
> SoC pin.
>
> For some other pins, the FPGA acts as a mux, and routes one pin (or the
> other one) to the header.
>
> The driver provides also a gpiochip. It requests SoC pins in GPIO mode,
> and drives them in tandem with FPGA pins (switch/mux direction).
>
> This commit adds support only for UP Squared board
>
> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>

From a pin control PoV this looks good:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij