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[24.6.151.244]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50cfae4asm92420035ad.106.2025.04.22.18.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 18:21:42 -0700 (PDT) Date: Tue, 22 Apr 2025 18:21:39 -0700 From: Joe Damato To: Harshitha Ramamurthy Cc: netdev@vger.kernel.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jeroendb@google.com, andrew+netdev@lunn.ch, willemb@google.com, ziweixiao@google.com, pkaligineedi@google.com, yyd@google.com, joshwash@google.com, shailend@google.com, linux@treblig.org, thostet@google.com, jfraker@google.com, horms@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 4/6] gve: Add rx hardware timestamp expansion Message-ID: Mail-Followup-To: Joe Damato , Harshitha Ramamurthy , netdev@vger.kernel.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jeroendb@google.com, andrew+netdev@lunn.ch, willemb@google.com, ziweixiao@google.com, pkaligineedi@google.com, yyd@google.com, joshwash@google.com, shailend@google.com, linux@treblig.org, thostet@google.com, jfraker@google.com, horms@kernel.org, linux-kernel@vger.kernel.org References: <20250418221254.112433-1-hramamurthy@google.com> <20250418221254.112433-5-hramamurthy@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250418221254.112433-5-hramamurthy@google.com> On Fri, Apr 18, 2025 at 10:12:52PM +0000, Harshitha Ramamurthy wrote: > From: John Fraker > > Allow the rx path to recover the high 32 bits of the full 64 bit rx > timestamp. > > Use the low 32 bits of the last synced nic time and the 32 bits of the > timestamp provided in the rx descriptor to generate a difference, which > is then applied to the last synced nic time to reconstruct the complete > 64-bit timestamp. > > This scheme remains accurate as long as no more than ~2 seconds have > passed between the last read of the nic clock and the timestamping > application of the received packet. > > Co-developed-by: Ziwei Xiao > Signed-off-by: Ziwei Xiao > Reviewed-by: Willem de Bruijn > Signed-off-by: John Fraker > Signed-off-by: Harshitha Ramamurthy > --- > drivers/net/ethernet/google/gve/gve_rx_dqo.c | 23 ++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/drivers/net/ethernet/google/gve/gve_rx_dqo.c b/drivers/net/ethernet/google/gve/gve_rx_dqo.c > index dcb0545baa50..483d188d33ab 100644 > --- a/drivers/net/ethernet/google/gve/gve_rx_dqo.c > +++ b/drivers/net/ethernet/google/gve/gve_rx_dqo.c > @@ -437,6 +437,29 @@ static void gve_rx_skb_hash(struct sk_buff *skb, > skb_set_hash(skb, le32_to_cpu(compl_desc->hash), hash_type); > } > > +/* Expand the hardware timestamp to the full 64 bits of width, and add it to the > + * skb. > + * > + * This algorithm works by using the passed hardware timestamp to generate a > + * diff relative to the last read of the nic clock. This diff can be positive or > + * negative, as it is possible that we have read the clock more recently than > + * the hardware has received this packet. To detect this, we use the high bit of > + * the diff, and assume that the read is more recent if the high bit is set. In > + * this case we invert the process. > + * > + * Note that this means if the time delta between packet reception and the last > + * clock read is greater than ~2 seconds, this will provide invalid results. > + */ > +static void __maybe_unused gve_rx_skb_hwtstamp(struct gve_rx_ring *rx, u32 hwts) > +{ > + s64 last_read = rx->gve->last_sync_nic_counter; Does this need a READ_ONCE to match the WRITE_ONCE in the previous patch ?