From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Sascha Bischoff <sascha.bischoff@arm.com>,
Timothy Hayes <timothy.hayes@arm.com>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
Mark Rutland <mark.rutland@arm.com>,
Jiri Slaby <jirislaby@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support
Date: Fri, 9 May 2025 10:35:25 +0200 [thread overview]
Message-ID: <aB2+TRSiGYL2eTWH@lpieralisi> (raw)
In-Reply-To: <aB230INCy2h7X1KY@lpieralisi>
On Fri, May 09, 2025 at 10:07:44AM +0200, Lorenzo Pieralisi wrote:
> On Thu, May 08, 2025 at 12:44:45PM +0200, Lorenzo Pieralisi wrote:
>
> [...]
>
> > I noticed that, if the irq_set_type() function is not implemented,
> > we don't execute (in __irq_set_trigger()):
> >
> > irq_settings_set_level(desc);
> > irqd_set(&desc->irq_data, IRQD_LEVEL);
>
> I don't get why the settings above are written only if the irqchip
> has an irq_set_type() method, maybe they should be updated in
> irqdomain code (?) where:
>
> irqd_set_trigger_type()
>
> is executed after creating the fwspec mapping ?
>
> Is it possible we never noticed because we have always had irqchips that
> do implement irq_set_type() ?
>
> Again, I don't know the history behind the IRQD_LEVEL flag so it is just
> a question, I'd need to get this clarified though please if I remove the
> PPI irq_set_type() callback.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/platforms/52xx/mpc52xx_pic.c?h=v6.15-rc5#n218
There are other examples in powerpc, this does not look right to me.
Lorenzo
> Thanks,
> Lorenzo
>
> > which in turn means that irqd_is_level_type(&desc->irq_data) is false
> > for PPIs (ie arch timers, despite being level interrupts).
> >
> > An immediate side effect is that they show as edge in:
> >
> > /proc/interrupts
> >
> > but that's just what I could notice.
> >
> > Should I set them myself in PPI translate/alloc functions ?
> >
> > Removing the irq_set_type() for PPIs does not seem so innocuous, it is a
> > bit complex to check all ramifications, please let me know if you spot
> > something I have missed.
> >
> > > > On the other hand, given that on GICv5 PPI handling mode is fixed,
> > > > do you think that in the ppi_irq_domain_ops.translate() callback,
> > > > I should check the type the firmware provided and fail the translation
> > > > if it does not match the HW hardcoded value ?
> > >
> > > Why? The fact that the firmware is wrong doesn't change the hardware
> > > integration. It just indicates that whoever wrote the firmware didn't
> > > read the documentation.
> > >
> > > Even more, I wonder what the benefit of having that information in the
> > > firmware tables if the only thing that matters in the immutable HW
> > > view. Yes, having it in the DT/ACPI simplifies the job of the kernel
> > > (only one format to parse). But it is overall useless information.
> >
> > Yes, that I agree but it would force firmware bindings to special case
> > PPIs to remove the type (#interrupt-cells and co.).
> >
> > From what I read I understand I must ignore the PPI type provided by
> > firmware.
> >
> > > > Obviously if firmware exposes the wrong type that's a firmware bug
> > > > but I was wondering whether it is better to fail the firmware-to-Linux
> > > > IRQ translation if the firmware provided type is wrong rather than carry
> > > > on pretending that the type is correct (I was abusing the irq_set_type()
> > > > callback to do just that - namely, check that the type provided by
> > > > firmware matches HW but I think that's the wrong place to put it).
> > >
> > > I don't think there is anything to do. Worse case, you spit a
> > > pr_warn_once() and carry on.
> >
> > Thanks,
> > Lorenzo
next prev parent reply other threads:[~2025-05-09 8:35 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-06 12:23 [PATCH v3 00/25] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 01/25] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-05-06 19:08 ` Rob Herring
2025-05-07 8:35 ` Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 02/25] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 03/25] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 04/25] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 05/25] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 06/25] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 07/25] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 08/25] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 09/25] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 10/25] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 11/25] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 12/25] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 13/25] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 14/25] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 15/25] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 16/25] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 17/25] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 18/25] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 19/25] arm64: Add support for GICv5 GSB barriers Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-05-06 15:00 ` Thomas Gleixner
2025-05-07 8:29 ` Lorenzo Pieralisi
2025-05-07 9:14 ` Marc Zyngier
2025-05-07 13:42 ` Thomas Gleixner
2025-05-07 13:52 ` Marc Zyngier
2025-05-07 14:57 ` Thomas Gleixner
2025-05-07 15:48 ` Lorenzo Pieralisi
2025-05-08 7:42 ` Lorenzo Pieralisi
2025-05-08 8:42 ` Marc Zyngier
2025-05-08 10:44 ` Lorenzo Pieralisi
2025-05-09 8:07 ` Lorenzo Pieralisi
2025-05-09 8:35 ` Lorenzo Pieralisi [this message]
2025-05-12 8:32 ` Marc Zyngier
2025-05-12 8:27 ` Marc Zyngier
2025-05-06 12:23 ` [PATCH v3 21/25] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 22/25] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-05-06 15:07 ` Thomas Gleixner
2025-05-07 8:30 ` Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 23/25] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 24/25] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-05-09 0:47 ` kernel test robot
2025-05-06 12:23 ` [PATCH v3 25/25] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
2025-05-06 14:05 ` [PATCH v3 00/25] Arm GICv5: Host driver implementation Marc Zyngier
2025-05-07 7:54 ` Lorenzo Pieralisi
2025-05-07 9:09 ` Marc Zyngier
2025-05-07 10:01 ` Lorenzo Pieralisi
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