[net PATCH 0/2] octeontx2-af: APR Mapping Fixes

[net PATCH 0/2] octeontx2-af: APR Mapping Fixes

[Geetha sowjanya]

This patch series includes fixes related to APR (LMT)
mapping and debugfs support.

Changes include:

Patch 1:Set LMT_ENA bit for APR table entries.
	Enables the LMT line for each PF/VF by setting
	the LMT_ENA bit in the APR_LMT_MAP_ENTRY_S
	structure.

Patch-2:Fix APR entry in debugfs
	The APR table was previously mapped using a fixed size,
	which could lead to incorrect mappings when the number
	of PFs and VFs differed from the assumed value.
	This patch updates the logic to calculate the APR table
	size dynamically, based on values from the APR_LMT_CFG
	register, ensuring correct representation in debugfs.

Geetha sowjanya (1):
   octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG

Subbaraya Sundeep (1):
  octeontx2-af: Set LMT_ENA bit for APR table entries

 .../ethernet/marvell/octeontx2/af/rvu_cn10k.c | 24 +++++++++++++++----
 .../marvell/octeontx2/af/rvu_debugfs.c        | 11 ++++++---
 2 files changed, 27 insertions(+), 8 deletions(-)

-- 
2.25.1

[net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table entries

[Geetha sowjanya]

From: Subbaraya Sundeep <sbhatta@marvell.com>

This patch enables the LMT line for a PF/VF by setting the
LMT_ENA bit in the APR_LMT_MAP_ENTRY_S structure.

Additionally, it simplifies the logic for calculating the
LMTST table index by consistently using the maximum
number of hw supported VFs (i.e., 256).

Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table").
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
 .../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
index 7fa98aeb3663..3838c04b78c2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
@@ -15,13 +15,17 @@
 #define LMT_TBL_OP_WRITE	1
 #define LMT_MAP_TABLE_SIZE	(128 * 1024)
 #define LMT_MAPTBL_ENTRY_SIZE	16
+#define LMT_MAX_VFS		256
+
+#define LMT_MAP_ENTRY_ENA      BIT_ULL(20)
+#define LMT_MAP_ENTRY_LINES    GENMASK_ULL(18, 16)
 
 /* Function to perform operations (read/write) on lmtst map table */
 static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
 			       int lmt_tbl_op)
 {
 	void __iomem *lmt_map_base;
-	u64 tbl_base;
+	u64 tbl_base, cfg;
 
 	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
 
@@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
 		*val = readq(lmt_map_base + index);
 	} else {
 		writeq((*val), (lmt_map_base + index));
+
+		cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
+		/* 2048 LMTLINES */
+		cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
+
+		writeq(cfg, (lmt_map_base + (index + 8)));
+
 		/* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
 		 * changes effective. Write 1 for flush and read is being used as a
 		 * barrier and sets up a data dependency. Write to 0 after a write
@@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
 #define LMT_MAP_TBL_W1_OFF  8
 static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
 {
-	return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
+	return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) +
 		(pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;
 }
 
-- 
2.25.1

Re: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table entries

[Michal Swiatkowski]

On Wed, May 21, 2025 at 11:38:33AM +0530, Geetha sowjanya wrote:
> From: Subbaraya Sundeep <sbhatta@marvell.com>
> 
> This patch enables the LMT line for a PF/VF by setting the
> LMT_ENA bit in the APR_LMT_MAP_ENTRY_S structure.
> 
> Additionally, it simplifies the logic for calculating the
> LMTST table index by consistently using the maximum
> number of hw supported VFs (i.e., 256).
> 
> Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table").
> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
> ---
>  .../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
> index 7fa98aeb3663..3838c04b78c2 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
> @@ -15,13 +15,17 @@
>  #define LMT_TBL_OP_WRITE	1
>  #define LMT_MAP_TABLE_SIZE	(128 * 1024)
>  #define LMT_MAPTBL_ENTRY_SIZE	16
> +#define LMT_MAX_VFS		256
> +
> +#define LMT_MAP_ENTRY_ENA      BIT_ULL(20)
> +#define LMT_MAP_ENTRY_LINES    GENMASK_ULL(18, 16)
>  
>  /* Function to perform operations (read/write) on lmtst map table */
>  static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
>  			       int lmt_tbl_op)
>  {
>  	void __iomem *lmt_map_base;
> -	u64 tbl_base;
> +	u64 tbl_base, cfg;
>  
>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
>  
> @@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
>  		*val = readq(lmt_map_base + index);
>  	} else {
>  		writeq((*val), (lmt_map_base + index));
> +
> +		cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
> +		/* 2048 LMTLINES */
> +		cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
> +
> +		writeq(cfg, (lmt_map_base + (index + 8)));
Is this 8 LMT_MAP_TBL_W1_OFF? It isn't obvious for me why +8, but I
don't know the driver, so maybe it should.

> +
>  		/* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
>  		 * changes effective. Write 1 for flush and read is being used as a
>  		 * barrier and sets up a data dependency. Write to 0 after a write
> @@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
>  #define LMT_MAP_TBL_W1_OFF  8
>  static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
>  {
> -	return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
> +	return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) +
>  		(pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;

Just nit/question, patch looks fine
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>

>  }
>  
> -- 
> 2.25.1

Re: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table entries

[Geethasowjanya Akula]

>-----Original Message-----
>From: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
>Sent: Wednesday, May 21, 2025 2:10 PM
>To: Geethasowjanya Akula <gakula@marvell.com>
>Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; kuba@kernel.org;
>davem@davemloft.net; pabeni@redhat.com; edumazet@google.com;
>andrew+netdev@lunn.ch; Sunil Kovvuri Goutham <sgoutham@marvell.com>;
>Subbaraya Sundeep Bhatta <sbhatta@marvell.com>; Hariprasad Kelam
><hkelam@marvell.com>
>Subject: [EXTERNAL] Re: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR
>table entries
>
>On Wed, May 21, 2025 at 11:38:33AM +0530, Geetha sowjanya wrote:
>> From: Subbaraya Sundeep <sbhatta@marvell.com>
>>
>> This patch enables the LMT line for a PF/VF by setting the LMT_ENA bit
>> in the APR_LMT_MAP_ENTRY_S structure.
>>
>> Additionally, it simplifies the logic for calculating the LMTST table
>> index by consistently using the maximum number of hw supported VFs
>> (i.e., 256).
>>
>> Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table").
>> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
>> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
>> ---
>>  .../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 15
>> +++++++++++++--
>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> index 7fa98aeb3663..3838c04b78c2 100644
>> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> @@ -15,13 +15,17 @@
>>  #define LMT_TBL_OP_WRITE	1
>>  #define LMT_MAP_TABLE_SIZE	(128 * 1024)
>>  #define LMT_MAPTBL_ENTRY_SIZE	16
>> +#define LMT_MAX_VFS		256
>> +
>> +#define LMT_MAP_ENTRY_ENA      BIT_ULL(20)
>> +#define LMT_MAP_ENTRY_LINES    GENMASK_ULL(18, 16)
>>
>>  /* Function to perform operations (read/write) on lmtst map table */
>> static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
>>  			       int lmt_tbl_op)
>>  {
>>  	void __iomem *lmt_map_base;
>> -	u64 tbl_base;
>> +	u64 tbl_base, cfg;
>>
>>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
>>
>> @@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32
>index, u64 *val,
>>  		*val = readq(lmt_map_base + index);
>>  	} else {
>>  		writeq((*val), (lmt_map_base + index));
>> +
>> +		cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
>> +		/* 2048 LMTLINES */
>> +		cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
>> +
>> +		writeq(cfg, (lmt_map_base + (index + 8)));
>Is this 8 LMT_MAP_TBL_W1_OFF? It isn't obvious for me why +8, but I don't
>know the driver, so maybe it should.
The APR table entry is 16B wide. The  ENTRY_ENA and ENTRY_LINES fields falls in upper 8B.
Hence doing +8.

Thanks,
Geetha.
>
>> +
>>  		/* Flushing the AP interceptor cache to make
>APR_LMT_MAP_ENTRY_S
>>  		 * changes effective. Write 1 for flush and read is being used as
>a
>>  		 * barrier and sets up a data dependency. Write to 0 after a
>write
>> @@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32
>> index, u64 *val,  #define LMT_MAP_TBL_W1_OFF  8  static u32
>> rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)  {
>> -	return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
>> +	return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) +
>>  		(pcifunc & RVU_PFVF_FUNC_MASK)) *
>LMT_MAPTBL_ENTRY_SIZE;
>
>Just nit/question, patch looks fine
>Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
>
>>  }
>>
>> --
>> 2.25.1

[net PATCH 2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG

[Geetha sowjanya]

The current implementation maps the APR table using a fixed size,
which can lead to incorrect mapping when the number of PFs and VFs
varies.
This patch corrects the mapping by calculating the APR table
size dynamically based on the values configured in the
APR_LMT_CFG register, ensuring accurate representation
of APR entries in debugfs.

Fixes: 0daa55d033b0 ("octeontx2-af: cn10k: debugfs for dumping LMTST map table").
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
 drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c |  9 ++++++---
 .../net/ethernet/marvell/octeontx2/af/rvu_debugfs.c   | 11 ++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
index 3838c04b78c2..4a3370a40dd8 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
@@ -13,7 +13,6 @@
 /* RVU LMTST */
 #define LMT_TBL_OP_READ		0
 #define LMT_TBL_OP_WRITE	1
-#define LMT_MAP_TABLE_SIZE	(128 * 1024)
 #define LMT_MAPTBL_ENTRY_SIZE	16
 #define LMT_MAX_VFS		256
 
@@ -26,10 +25,14 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
 {
 	void __iomem *lmt_map_base;
 	u64 tbl_base, cfg;
+	int pfs, vfs;
 
 	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
+	cfg  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
+	vfs = 1 << (cfg & 0xF);
+	pfs = 1 << ((cfg >> 4) & 0x7);
 
-	lmt_map_base = ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE);
+	lmt_map_base = ioremap_wc(tbl_base, pfs * vfs * LMT_MAPTBL_ENTRY_SIZE);
 	if (!lmt_map_base) {
 		dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
 		return -ENOMEM;
@@ -80,7 +83,7 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc,
 
 	mutex_lock(&rvu->rsrc_lock);
 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova);
-	pf = rvu_get_pf(pcifunc) & 0x1F;
+	pf = rvu_get_pf(pcifunc) & RVU_PFVF_PF_MASK;
 	val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 |
 	      ((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF);
 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
index a1f9ec03c2ce..c827da626471 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
@@ -553,6 +553,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
 	u64 lmt_addr, val, tbl_base;
 	int pf, vf, num_vfs, hw_vfs;
 	void __iomem *lmt_map_base;
+	int apr_pfs, apr_vfs;
 	int buf_size = 10240;
 	size_t off = 0;
 	int index = 0;
@@ -568,8 +569,12 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
 		return -ENOMEM;
 
 	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
+	val  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
+	apr_vfs = 1 << (val & 0xF);
+	apr_pfs = 1 << ((val >> 4) & 0x7);
 
-	lmt_map_base = ioremap_wc(tbl_base, 128 * 1024);
+	lmt_map_base = ioremap_wc(tbl_base, apr_pfs * apr_vfs *
+				  LMT_MAPTBL_ENTRY_SIZE);
 	if (!lmt_map_base) {
 		dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
 		kfree(buf);
@@ -591,7 +596,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
 		off += scnprintf(&buf[off], buf_size - 1 - off, "PF%d  \t\t\t",
 				    pf);
 
-		index = pf * rvu->hw->total_vfs * LMT_MAPTBL_ENTRY_SIZE;
+		index = pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE;
 		off += scnprintf(&buf[off], buf_size - 1 - off, " 0x%llx\t\t",
 				 (tbl_base + index));
 		lmt_addr = readq(lmt_map_base + index);
@@ -604,7 +609,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
 		/* Reading num of VFs per PF */
 		rvu_get_pf_numvfs(rvu, pf, &num_vfs, &hw_vfs);
 		for (vf = 0; vf < num_vfs; vf++) {
-			index = (pf * rvu->hw->total_vfs * 16) +
+			index = (pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE) +
 				((vf + 1)  * LMT_MAPTBL_ENTRY_SIZE);
 			off += scnprintf(&buf[off], buf_size - 1 - off,
 					    "PF%d:VF%d  \t\t", pf, vf);
-- 
2.25.1

Re: [net PATCH 2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG

[Michal Swiatkowski]

On Wed, May 21, 2025 at 11:38:34AM +0530, Geetha sowjanya wrote:
> The current implementation maps the APR table using a fixed size,
> which can lead to incorrect mapping when the number of PFs and VFs
> varies.
> This patch corrects the mapping by calculating the APR table
> size dynamically based on the values configured in the
> APR_LMT_CFG register, ensuring accurate representation
> of APR entries in debugfs.
> 
> Fixes: 0daa55d033b0 ("octeontx2-af: cn10k: debugfs for dumping LMTST map table").
> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
> ---
>  drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c |  9 ++++++---
>  .../net/ethernet/marvell/octeontx2/af/rvu_debugfs.c   | 11 ++++++++---
>  2 files changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
> index 3838c04b78c2..4a3370a40dd8 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
> @@ -13,7 +13,6 @@
>  /* RVU LMTST */
>  #define LMT_TBL_OP_READ		0
>  #define LMT_TBL_OP_WRITE	1
> -#define LMT_MAP_TABLE_SIZE	(128 * 1024)
>  #define LMT_MAPTBL_ENTRY_SIZE	16
>  #define LMT_MAX_VFS		256
>  
> @@ -26,10 +25,14 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
>  {
>  	void __iomem *lmt_map_base;
>  	u64 tbl_base, cfg;
> +	int pfs, vfs;
>  
>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
> +	cfg  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
> +	vfs = 1 << (cfg & 0xF);
> +	pfs = 1 << ((cfg >> 4) & 0x7);
>  
> -	lmt_map_base = ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE);
> +	lmt_map_base = ioremap_wc(tbl_base, pfs * vfs * LMT_MAPTBL_ENTRY_SIZE);
>  	if (!lmt_map_base) {
>  		dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
>  		return -ENOMEM;
> @@ -80,7 +83,7 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc,
>  
>  	mutex_lock(&rvu->rsrc_lock);
>  	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova);
> -	pf = rvu_get_pf(pcifunc) & 0x1F;
> +	pf = rvu_get_pf(pcifunc) & RVU_PFVF_PF_MASK;
>  	val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 |
>  	      ((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF);
>  	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val);
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
> index a1f9ec03c2ce..c827da626471 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
> @@ -553,6 +553,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
>  	u64 lmt_addr, val, tbl_base;
>  	int pf, vf, num_vfs, hw_vfs;
>  	void __iomem *lmt_map_base;
> +	int apr_pfs, apr_vfs;
>  	int buf_size = 10240;
>  	size_t off = 0;
>  	int index = 0;
> @@ -568,8 +569,12 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
>  		return -ENOMEM;
>  
>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
> +	val  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
> +	apr_vfs = 1 << (val & 0xF);
> +	apr_pfs = 1 << ((val >> 4) & 0x7);
>  
> -	lmt_map_base = ioremap_wc(tbl_base, 128 * 1024);
> +	lmt_map_base = ioremap_wc(tbl_base, apr_pfs * apr_vfs *
> +				  LMT_MAPTBL_ENTRY_SIZE);

As it is the same as in lmtst_map_table_ops() I think you can move whole
to a new function.

rvu_ioremap_wc(rvu, base, size);

or sth like that. It isn't strong opinion. Rest looks fine, thanks.

>  	if (!lmt_map_base) {
>  		dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
>  		kfree(buf);
> @@ -591,7 +596,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
>  		off += scnprintf(&buf[off], buf_size - 1 - off, "PF%d  \t\t\t",
>  				    pf);
>  
> -		index = pf * rvu->hw->total_vfs * LMT_MAPTBL_ENTRY_SIZE;
> +		index = pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE;
>  		off += scnprintf(&buf[off], buf_size - 1 - off, " 0x%llx\t\t",
>  				 (tbl_base + index));
>  		lmt_addr = readq(lmt_map_base + index);
> @@ -604,7 +609,7 @@ static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
>  		/* Reading num of VFs per PF */
>  		rvu_get_pf_numvfs(rvu, pf, &num_vfs, &hw_vfs);
>  		for (vf = 0; vf < num_vfs; vf++) {
> -			index = (pf * rvu->hw->total_vfs * 16) +
> +			index = (pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE) +
>  				((vf + 1)  * LMT_MAPTBL_ENTRY_SIZE);
>  			off += scnprintf(&buf[off], buf_size - 1 - off,
>  					    "PF%d:VF%d  \t\t", pf, vf);
> -- 
> 2.25.1

Re: [net PATCH 2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG

[Geethasowjanya Akula]

>-----Original Message-----
>From: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
>Sent: Wednesday, May 21, 2025 2:06 PM
>To: Geethasowjanya Akula <gakula@marvell.com>
>Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; kuba@kernel.org;
>davem@davemloft.net; pabeni@redhat.com; edumazet@google.com;
>andrew+netdev@lunn.ch; Sunil Kovvuri Goutham <sgoutham@marvell.com>;
>Subbaraya Sundeep Bhatta <sbhatta@marvell.com>; Hariprasad Kelam
><hkelam@marvell.com>
>Subject: [EXTERNAL] Re: [net PATCH 2/2] octeontx2-af: Fix APR entry mapping
>based on APR_LMT_CFG
>On Wed, May 21, 2025 at 11:38:34AM +0530, Geetha sowjanya wrote:
>> The current implementation maps the APR table using a fixed size,
>> which can lead to incorrect mapping when the number of PFs and VFs
>> varies.
>> This patch corrects the mapping by calculating the APR table size
>> dynamically based on the values configured in the APR_LMT_CFG
>> register, ensuring accurate representation of APR entries in debugfs.
>>
>> Fixes: 0daa55d033b0 ("octeontx2-af: cn10k: debugfs for dumping LMTST
>map table").
>> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
>> ---
>>  drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c |  9 ++++++---
>>  .../net/ethernet/marvell/octeontx2/af/rvu_debugfs.c   | 11 ++++++++---
>>  2 files changed, 14 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> index 3838c04b78c2..4a3370a40dd8 100644
>> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> @@ -13,7 +13,6 @@
>>  /* RVU LMTST */
>>  #define LMT_TBL_OP_READ		0
>>  #define LMT_TBL_OP_WRITE	1
>> -#define LMT_MAP_TABLE_SIZE	(128 * 1024)
>>  #define LMT_MAPTBL_ENTRY_SIZE	16
>>  #define LMT_MAX_VFS		256
>>
>> @@ -26,10 +25,14 @@ static int lmtst_map_table_ops(struct rvu *rvu,
>> u32 index, u64 *val,  {
>>  	void __iomem *lmt_map_base;
>>  	u64 tbl_base, cfg;
>> +	int pfs, vfs;
>>
>>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
>> +	cfg  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
>> +	vfs = 1 << (cfg & 0xF);
>> +	pfs = 1 << ((cfg >> 4) & 0x7);
>>
>> -	lmt_map_base = ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE);
>> +	lmt_map_base = ioremap_wc(tbl_base, pfs * vfs *
>> +LMT_MAPTBL_ENTRY_SIZE);
>>  	if (!lmt_map_base) {
>>  		dev_err(rvu->dev, "Failed to setup lmt map table
>mapping!!\n");
>>  		return -ENOMEM;
>> @@ -80,7 +83,7 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16
>> pcifunc,
>>
>>  	mutex_lock(&rvu->rsrc_lock);
>>  	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova);
>> -	pf = rvu_get_pf(pcifunc) & 0x1F;
>> +	pf = rvu_get_pf(pcifunc) & RVU_PFVF_PF_MASK;
>>  	val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 |
>>  	      ((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF);
>>  	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val);
>diff --git
>> a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
>> b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
>> index a1f9ec03c2ce..c827da626471 100644
>> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
>> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
>> @@ -553,6 +553,7 @@ static ssize_t
>rvu_dbg_lmtst_map_table_display(struct file *filp,
>>  	u64 lmt_addr, val, tbl_base;
>>  	int pf, vf, num_vfs, hw_vfs;
>>  	void __iomem *lmt_map_base;
>> +	int apr_pfs, apr_vfs;
>>  	int buf_size = 10240;
>>  	size_t off = 0;
>>  	int index = 0;
>> @@ -568,8 +569,12 @@ static ssize_t
>rvu_dbg_lmtst_map_table_display(struct file *filp,
>>  		return -ENOMEM;
>>
>>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
>> +	val  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
>> +	apr_vfs = 1 << (val & 0xF);
>> +	apr_pfs = 1 << ((val >> 4) & 0x7);
>>
>> -	lmt_map_base = ioremap_wc(tbl_base, 128 * 1024);
>> +	lmt_map_base = ioremap_wc(tbl_base, apr_pfs * apr_vfs *
>> +				  LMT_MAPTBL_ENTRY_SIZE);
>
>As it is the same as in lmtst_map_table_ops() I think you can move whole to a
>new function.
>
>rvu_ioremap_wc(rvu, base, size);
>
>or sth like that. It isn't strong opinion. Rest looks fine, thanks.
Will address your suggestion in new patch along with other code enhancement.
Thanks for the feedback.

Geetha.
>
>>  	if (!lmt_map_base) {
>>  		dev_err(rvu->dev, "Failed to setup lmt map table
>mapping!!\n");
>>  		kfree(buf);
>> @@ -591,7 +596,7 @@ static ssize_t
>rvu_dbg_lmtst_map_table_display(struct file *filp,
>>  		off += scnprintf(&buf[off], buf_size - 1 - off, "PF%d  \t\t\t",
>>  				    pf);
>>
>> -		index = pf * rvu->hw->total_vfs * LMT_MAPTBL_ENTRY_SIZE;
>> +		index = pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE;
>>  		off += scnprintf(&buf[off], buf_size - 1 - off, " 0x%llx\t\t",
>>  				 (tbl_base + index));
>>  		lmt_addr = readq(lmt_map_base + index); @@ -604,7 +609,7
>@@ static
>> ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp,
>>  		/* Reading num of VFs per PF */
>>  		rvu_get_pf_numvfs(rvu, pf, &num_vfs, &hw_vfs);
>>  		for (vf = 0; vf < num_vfs; vf++) {
>> -			index = (pf * rvu->hw->total_vfs * 16) +
>> +			index = (pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE) +
>>  				((vf + 1)  * LMT_MAPTBL_ENTRY_SIZE);
>>  			off += scnprintf(&buf[off], buf_size - 1 - off,
>>  					    "PF%d:VF%d  \t\t", pf, vf);
>> --
>> 2.25.1

Re: [net PATCH 2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG

[Paolo Abeni]

On 5/21/25 2:07 PM, Geethasowjanya Akula wrote:
>> -----Original Message-----
>> From: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
>> Sent: Wednesday, May 21, 2025 2:06 PM
>>> @@ -568,8 +569,12 @@ static ssize_t
>> rvu_dbg_lmtst_map_table_display(struct file *filp,
>>>  		return -ENOMEM;
>>>
>>>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
>>> +	val  = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
>>> +	apr_vfs = 1 << (val & 0xF);
>>> +	apr_pfs = 1 << ((val >> 4) & 0x7);
>>>
>>> -	lmt_map_base = ioremap_wc(tbl_base, 128 * 1024);
>>> +	lmt_map_base = ioremap_wc(tbl_base, apr_pfs * apr_vfs *
>>> +				  LMT_MAPTBL_ENTRY_SIZE);
>>
>> As it is the same as in lmtst_map_table_ops() I think you can move whole to a
>> new function.
>>
>> rvu_ioremap_wc(rvu, base, size);
>>
>> or sth like that. It isn't strong opinion. Rest looks fine, thanks.
> Will address your suggestion in new patch along with other code enhancement.

FTR, I'm fine with a net-next follow-up.

Cheers,

Paolo

Re: [net PATCH 0/2] octeontx2-af: APR Mapping Fixes

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net.git (main)
by Paolo Abeni <pabeni@redhat.com>:

On Wed, 21 May 2025 11:38:32 +0530 you wrote:
> This patch series includes fixes related to APR (LMT)
> mapping and debugfs support.
> 
> Changes include:
> 
> Patch 1:Set LMT_ENA bit for APR table entries.
> 	Enables the LMT line for each PF/VF by setting
> 	the LMT_ENA bit in the APR_LMT_MAP_ENTRY_S
> 	structure.
> 
> [...]

Here is the summary with links:
  - [net,1/2] octeontx2-af: Set LMT_ENA bit for APR table entries
    https://git.kernel.org/netdev/net/c/0eefa27b4933
  - [net,2/2] octeontx2-af: Fix APR entry mapping based on APR_LMT_CFG
    https://git.kernel.org/netdev/net/c/a6ae7129819a

You are awesome, thank you!
-- 
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