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X-CSE-ConnectionGUID: /NlwuTENTMyvUoQTCQk15g== X-CSE-MsgGUID: jYIgMtlCTIyhaiPH9tW3Ag== X-IronPort-AV: E=McAfee;i="6700,10204,11440"; a="72345621" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="72345621" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 08:33:04 -0700 X-CSE-ConnectionGUID: /0j+tz1wRYKNB1/qh7Axyg== X-CSE-MsgGUID: osH+72QJRYGme7yAqVUxjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="141046554" Received: from smile.fi.intel.com ([10.237.72.52]) by orviesa008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 08:33:00 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.98.2) (envelope-from ) id 1uHlRB-00000003fEh-41bz; Wed, 21 May 2025 18:32:57 +0300 Date: Wed, 21 May 2025 18:32:57 +0300 From: Andy Shevchenko To: Thomas Richard Cc: Linus Walleij , Bartosz Golaszewski , Geert Uytterhoeven , Kees Cook , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, DanieleCleri@aaeon.eu, GaryWang@aaeon.com.tw, linux-hardening@vger.kernel.org Subject: Re: [PATCH v6 12/12] pinctrl: Add pin controller driver for AAEON UP boards Message-ID: References: <20250520-aaeon-up-board-pinctrl-support-v6-0-dcb3756be3c6@bootlin.com> <20250520-aaeon-up-board-pinctrl-support-v6-12-dcb3756be3c6@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250520-aaeon-up-board-pinctrl-support-v6-12-dcb3756be3c6@bootlin.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Tue, May 20, 2025 at 03:28:36PM +0200, Thomas Richard wrote: > This enables the pin control support of the onboard FPGA on AAEON UP > boards. > > This FPGA acts as a level shifter between the Intel SoC pins and the pin > header, and also as a mux or switch. > > +---------+ +--------------+ +---+ > | | | | | > | PWM0 | \ | | H | > |----------|------ \-----|-------------| E | > | I2C0_SDA | | | A | > Intel SoC |----------|------\ | | D | > | GPIO0 | \------|-------------| E | > |----------|------ | | R | > | | FPGA | | | > ----------+ +--------------+ +---+ > > For most of the pins, the FPGA opens/closes a switch to enable/disable > the access to the SoC pin from a pin header. > Each switch, has a direction flag that is set depending the status of the > SoC pin. > > For some other pins, the FPGA acts as a mux, and routes one pin (or the > other one) to the header. > > The driver also provides a GPIO chip. It requests SoC pins in GPIO mode, > and drives them in tandem with FPGA pins (switch/mux direction). > > This commit adds support only for UP Squared board. ... > +static int upboard_pinctrl_pin_get_mode(struct pinctrl_dev *pctldev, unsigned int pin) > +{ > + struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > + struct upboard_pin *p = &pctrl->pins[pin]; > + unsigned int val; > + int ret; > + > + if (p->funcbit) { > + ret = regmap_field_read(p->funcbit, &val); > + if (ret) > + return ret; > + if (val) > + return UPBOARD_PIN_MODE_FUNCTION; > + } > + > + ret = regmap_field_read(p->enbit, &val); > + if (ret) > + return ret; > + if (!val) > + return UPBOARD_PIN_MODE_DISABLED; > + > + ret = regmap_field_read(p->dirbit, &val); > + if (ret) > + return ret; > + > + return val ? UPBOARD_PIN_MODE_GPIO_IN : UPBOARD_PIN_MODE_GPIO_OUT; > +} > + > +static void upboard_pinctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, > + unsigned int offset) > +{ > + int ret; > + > + ret = upboard_pinctrl_pin_get_mode(pctldev, offset); > + if (ret == UPBOARD_PIN_MODE_FUNCTION) > + seq_puts(s, "mode function "); > + else if (ret == UPBOARD_PIN_MODE_DISABLED) > + seq_puts(s, "HIGH-Z "); > + else > + seq_printf(s, "GPIO (%s) ", str_input_output(ret == UPBOARD_PIN_MODE_GPIO_IN)); Actually this should be else if (ret < 0) seq_printf(s, "N/A "); // or similar text else seq_printf(s, "GPIO (%s) ", str_input_output(ret == UPBOARD_PIN_MODE_GPIO_IN)); as the above may return a negative error code which is not listed here. > +} With the above being addressed, Reviewed-by: Andy Shevchenko ... Thanks for doing this driver, eventually we will have it working out-of-the-box. Do you have any plans for enabling HSI and SIM card slot on UP Squared 7000? -- With Best Regards, Andy Shevchenko