Re: [PATCH v4 14/26] arm64/sysreg: Add ICH_HFGITR_EL2

Jonathan Cameron
2025-05-28T11:28:31Z

On Tue, 13 May 2025 19:48:07 +0200
Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:

> Add ICH_HFGITR_EL2 register description to sysreg.
>
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>

Hi Lorenzo,

> ---
> arch/arm64/tools/sysreg | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 0927754d9fe2c5addbd9693d83b7324f1af66d3e..d2f53fb7929c69895fe8a21ba625d058a844d447 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -3616,6 +3616,21 @@ Res0 1
> Field 0 ICC_APR_EL1
> EndSysreg
>
> +Sysreg ICH_HFGITR_EL2 3 4 12 9 7
> +Res0 63:11
> +Field 10 GICRCDNMIA
> +Field 9 GICRCDIA
> +Field 8 GICCDDI
> +Field 7 GICCDEOI
> +Field 6 GICCDHM
> +Field 5 GICCRDRCFG

GICCDRCFG in the spec. (you have a bonus R)

Of course the real question was what am I avoiding that made checking these
against the spec feel like a good idea? :)

FWIW with that fixed,
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
for patches 2 to 14.

> +Field 4 GICCDPEND
> +Field 3 GICCDAFF
> +Field 2 GICCDPRI
> +Field 1 GICCDDIS
> +Field 0 GICCDEN
> +EndSysreg
> +
> Sysreg ICH_HCR_EL2 3 4 12 11 0
> Res0 63:32
> Field 31:27 EOIcount
>