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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f39ef81csm33273325e9.34.2025.05.14.08.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 08:21:12 -0700 (PDT) Date: Wed, 14 May 2025 17:21:10 +0200 From: Daniel Lezcano To: Ben Zong-You Xie Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tglx@linutronix.de, prabhakar.mahadev-lad.rj@bp.renesas.com, geert+renesas@glider.be, magnus.damm@gmail.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, tim609@andestech.com, Conor Dooley Subject: Re: [PATCH v4 5/9] dt-bindings: timer: add Andes machine timer Message-ID: References: <20250514095350.3765716-1-ben717@andestech.com> <20250514095350.3765716-6-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250514095350.3765716-6-ben717@andestech.com> On Wed, May 14, 2025 at 05:53:46PM +0800, Ben Zong-You Xie wrote: > Add the DT binding documentation for Andes machine timer. > > The RISC-V architecture defines a machine timer that provides a real-time > counter and generates timer interrupts. Andes machiner timer (PLMT0) is > the implementation of the machine timer, and it contains memory-mapped > registers (mtime and mtimecmp). This device supports up to 32 cores. > > Acked-by: Conor Dooley > Signed-off-by: Ben Zong-You Xie > --- The patch does not apply on my tree due to conflict with other patches of the series on the MAINTAINER file. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog