Re: [PATCH v10 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR

[Ingo Molnar <mingo@kernel.org>]

* Mario Limonciello <superm1@kernel.org> wrote:

> From: Perry Yuan <perry.yuan@amd.com>
> 
> Introduces new MSR registers for AMD hardware feedback support.
> These registers enable the system to provide workload classification
> and configuration capabilities.
> 
> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
> Signed-off-by: Perry Yuan <perry.yuan@amd.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>  arch/x86/include/asm/msr-index.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index b7dded3c81132..8e6db9a9f53c0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -732,6 +732,11 @@
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
>  
> +/* AMD Hardware Feedback Support MSRs */
> +#define AMD_WORKLOAD_CLASS_CONFIG      0xc0000500
> +#define AMD_WORKLOAD_CLASS_ID          0xc0000501
> +#define AMD_WORKLOAD_HRST              0xc0000502

Can we follow the existing pattern of MSR_AMD64_* or MSR_AMD_* that 99% 
of the indices in this header are following?

Thanks,

	Ingo