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X-CSE-ConnectionGUID: 1mmDWOJJQauiHCwjedfT4w== X-CSE-MsgGUID: DaaWwTvbSwW8MnXukLdFPA== X-IronPort-AV: E=McAfee;i="6700,10204,11446"; a="61431119" X-IronPort-AV: E=Sophos;i="6.15,319,1739865600"; d="scan'208";a="61431119" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2025 11:49:52 -0700 X-CSE-ConnectionGUID: NTG3c+mbSlWEHG5NEwB8JA== X-CSE-MsgGUID: ldVFg4/LSoqXZ5tLnXnV0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,319,1739865600"; d="scan'208";a="148212316" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa005.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2025 11:49:47 -0700 Date: Tue, 27 May 2025 21:49:43 +0300 From: Raag Jadav To: "Usyskin, Alexander" Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , "De Marchi, Lucas" , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , "Vivi, Rodrigo" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , "Poosa, Karthik" , "Abliyev, Reuven" , "Weil, Oren jer" , "linux-mtd@lists.infradead.org" , "intel-xe@lists.freedesktop.org" , "dri-devel@lists.freedesktop.org" , "intel-gfx@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v10 05/10] mtd: intel-dg: align 64bit read and write Message-ID: References: <20250515133345.2805031-1-alexander.usyskin@intel.com> <20250515133345.2805031-6-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, May 27, 2025 at 11:33:10AM +0530, Usyskin, Alexander wrote: > > Subject: Re: [PATCH v10 05/10] mtd: intel-dg: align 64bit read and write > > > > On Thu, May 15, 2025 at 04:33:40PM +0300, Alexander Usyskin wrote: > > > GSC NVM controller HW errors on quad access overlapping 1K border. > > > Align 64bit read and write to avoid readq/writeq over 1K border. > > > > > > Acked-by: Miquel Raynal > > > Signed-off-by: Alexander Usyskin > > > --- > > > drivers/mtd/devices/mtd_intel_dg.c | 35 > > ++++++++++++++++++++++++++++++ > > > 1 file changed, 35 insertions(+) > > > > > > diff --git a/drivers/mtd/devices/mtd_intel_dg.c > > b/drivers/mtd/devices/mtd_intel_dg.c > > > index eedc0974bb5b..2f32ed311ffd 100644 > > > --- a/drivers/mtd/devices/mtd_intel_dg.c > > > +++ b/drivers/mtd/devices/mtd_intel_dg.c > > > @@ -246,6 +246,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, > > u8 region, > > > len_s -= to_shift; > > > } > > > > > > + if (!IS_ALIGNED(to, sizeof(u64)) && > > > + ((to ^ (to + len_s)) & GENMASK(31, 10))) { > > > + /* > > > + * Workaround reads/writes across 1k-aligned addresses > > > + * (start u32 before 1k, end u32 after) > > > + * as this fails on hardware. > > > > If there's a spec definition, we usually mention workarounds with > > Wa_ID:platform so that they're easy to track. intel_workarounds.c > > is good reference for it. > > > There is nothing in spec that I can find. > Not sure that i can formalize i as workaround. I'm a bit uninformed about the history here, but in any case I'm fine as long as the maintainers are okay with it. Raag