[PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x

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* [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
@ 2024-10-18 20:53 jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 1/5] net: stmmac: Add snps_id, dev_id to struct plat_stmmacenet_data jitendra.vegiraju
                   ` (6 more replies)
  0 siblings, 7 replies; 19+ messages in thread
From: jitendra.vegiraju @ 2024-10-18 20:53 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, jitendra.vegiraju, bcm-kernel-feedback-list,
	richardcochran, ast, daniel, hawk, john.fastabend, fancer.lancer,
	rmk+kernel, ahalaney, xiaolei.wang, rohan.g.thomas,
	Jianheng.Zhang, linux-kernel, linux-stm32, linux-arm-kernel, bpf,
	andrew, linux, horms, florian.fainelli, quic_abchauha

From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>

This patchset adds basic PCI ethernet device driver support for Broadcom
BCM8958x Automotive Ethernet switch SoC devices.

This SoC device has PCIe ethernet MAC attached to an integrated ethernet
switch using XGMII interface. The PCIe ethernet controller is presented to
the Linux host as PCI network device.

The following block diagram gives an overview of the application.
             +=================================+
             |       Host CPU/Linux            |
             +=================================+
                        || PCIe
                        ||
        +==========================================+
        |           +--------------+               |
        |           | PCIE Endpoint|               |
        |           | Ethernet     |               |
        |           | Controller   |               |
        |           |   DMA        |               |
        |           +--------------+               |
        |           |   MAC        |   BCM8958X    |
        |           +--------------+   SoC         |
        |               || XGMII                   |
        |               ||                         |
        |           +--------------+               |
        |           | Ethernet     |               |
        |           | switch       |               |
        |           +--------------+               |
        |             || || || ||                  |
        +==========================================+
                      || || || || More external interfaces

The MAC block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
MAC IP introduces new DMA architecture called Hyper-DMA for virtualization
scalability.

Driver functionality specific to new MAC (DW25GMAC) is implemented in
new file dw25gmac.c.

Management of integrated ethernet switch on this SoC is not handled by
the PCIe interface.
This SoC device has PCIe ethernet MAC directly attached to an integrated
ethernet switch using XGMII interface.

v5->v6:
   Change summary to address comments/suggestions by Serge Semin.
   Patch1:
     Removed the comlexity of hdma mapping in previous patch series and
     use static DMA mapping.
     Renamed plat_stmmacenet_data::snps_dev_id as dev_id and moved to
     the beginning of the struct.
   Patch2:
     Added dw25gmac_get_hw_feature() for dw25gmac.
     Use static one-to-one VDMA-TC-PDMA mapping.
   Patch4:
     Remove usage of plat_stmmacenet_data::msi_*_vec variables for
     interrupt vector initialization.
     Change phy_interface type to XGMII.
     Cleanup unused macros.
     
v4->v5:
   Summary of changes in this patch series:
   As suggested by Serge Semin, defined common setup function for dw25gmac.
   To accommodate early adopter DW25GMAC used in BCM8958x device, provide
   a mechanism to override snps_id and snps_dev_id used for driver entry
   matching in hwif.c

   Patch1:
     Added plat_stmmacenet_data::snps_id,snps_dev_id fields - Serge Semin
   Patch2:
     Define common setup function for dw25gmac_setup() - Serge Semin
     Support DW25GMAC IPs with varying VDMA/PDMA count - Abhishek Chauhan
     Allocate and initialize hdma mapping configuration data dynamically
     based on device's VDMA/PDMA feature capabilities in dw25gmac_setup().
     Spelling errors in commit log, lower case 0x for hex -Amit Singh Tomar
   Patch3:
     Glue support in hwif.c for DW25GMAC in hwif.c - Serge Semin
     Provide an option to override snps_id and snps_dev_id when the device
     reports version info not conformant with driver's expectations as is
     the case with BCM8958x device. - Serge Semin
   Patch4:
     Remove setup function in the glue driver - Serge Semin
     Remove unnecessary calls pci_enable_device() and pci_set_master()
     in dwxgmac_brcm_pci_resume() - Jakub Kicinski
     Merge variable definitions to single line - Amit Singh Tomar
    https://lore.kernel.org/netdev/20240904054815.1341712-1-jitendra.vegiraju@broadcom.com/
   
v3->v4:
   Based on Serge's questions, received a confirmation from Synopsys that
   the MAC IP is indeed the new 25GMAC design.
   Renamed all references of XGMAC4 to 25GMAC.
   The patch series is rearranged slightly as follows.
   Patch1 (new): Define HDMA mapping data structure in kernel's stmmac.h
   Patch2 (v3 Patch1): Adds dma_ops for dw25gmac in stmmac core
       Renamed new files dwxgmac4.* to dw25gmac.* - Serge Semin
       Defined new Synopsis version and device id macros for DW25GMAC.
       Converted bit operations to FIELD_PREP macros - Russell King
       Moved hwif.h to this patch, Sparse flagged warning - Simon Horman
       Defined macros for hardcoded values TDPS etc - Serge Semin
       Read number of PDMAs/VDMAs from hardware - Serge Semin
   Patch3 (v3 Patch2): Hooks in hardware interface handling for dw25gmac
       Resolved user_version quirks questions - Serge, Russell, Andrew
       Added new stmmac_hw entry for DW25GMAC. - Serge
       Added logic to override synopsis_dev_id by glue driver.
   Patch4 (v3 Patch3): Adds PCI driver for BCM8958x device
       Define bitmmap macros for hardcoded values - Andrew Lunn
       Added per device software node - Andrew Lunn
   Patch5(new/split): Adds BCM8958x driver to build system
   https://lore.kernel.org/netdev/20240814221818.2612484-1-jitendra.vegiraju@broadcom.com/

v2->v3:
   Addressed v2 comments from Andrew, Jakub, Russel and Simon.
   Based on suggestion by Russel and Andrew, added software node to create
   phylink in fixed-link mode.
   Moved dwxgmac4 specific functions to new files dwxgmac4.c and dwxgmac4.h
   in stmmac core module.
   Reorganized the code to use the existing glue logic support for xgmac in
   hwif.c and override ops functions for dwxgmac4 specific functions.
   The patch is split into three parts.
     Patch#1 Adds dma_ops for dwxgmac4 in stmmac core
     Patch#2 Hooks in the hardware interface handling for dwxgmac4
     Patch#3 Adds PCI driver for BCM8958x device
   https://lore.kernel.org/netdev/20240802031822.1862030-1-jitendra.vegiraju@broadcom.com/

v1->v2:
   Minor fixes to address coding style issues.
   Sent v2 too soon by mistake, without waiting for review comments.
   Received feedback on this version.
   https://lore.kernel.org/netdev/20240511015924.41457-1-jitendra.vegiraju@broadcom.com/

v1:  
   https://lore.kernel.org/netdev/20240510000331.154486-1-jitendra.vegiraju@broadcom.com/

Jitendra Vegiraju (5):
  Add snps_id, dev_id to struct plat_stmmacenet_data
  Add basic dw25gmac support in stmmac core
  Integrate dw25gmac into stmmac hwif handling
  Add PCI driver support for BCM8958x
  Add BCM8958x driver to build system

 MAINTAINERS                                   |   8 +
 drivers/net/ethernet/stmicro/stmmac/Kconfig   |  11 +
 drivers/net/ethernet/stmicro/stmmac/Makefile  |   3 +-
 drivers/net/ethernet/stmicro/stmmac/common.h  |   4 +
 .../net/ethernet/stmicro/stmmac/dw25gmac.c    | 161 ++++++
 .../net/ethernet/stmicro/stmmac/dw25gmac.h    |  92 ++++
 .../net/ethernet/stmicro/stmmac/dwmac-brcm.c  | 478 ++++++++++++++++++
 .../net/ethernet/stmicro/stmmac/dwxgmac2.h    |   1 +
 .../ethernet/stmicro/stmmac/dwxgmac2_core.c   |  42 ++
 .../ethernet/stmicro/stmmac/dwxgmac2_dma.c    |  52 ++
 drivers/net/ethernet/stmicro/stmmac/hwif.c    |  26 +-
 drivers/net/ethernet/stmicro/stmmac/hwif.h    |   1 +
 .../net/ethernet/stmicro/stmmac/stmmac_main.c |  26 +
 include/linux/stmmac.h                        |   2 +
 14 files changed, 905 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c

-- 
2.34.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH net-next v6 1/5] net: stmmac: Add snps_id, dev_id to struct plat_stmmacenet_data
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
@ 2024-10-18 20:53 ` jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core jitendra.vegiraju
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 19+ messages in thread
From: jitendra.vegiraju @ 2024-10-18 20:53 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, jitendra.vegiraju, bcm-kernel-feedback-list,
	richardcochran, ast, daniel, hawk, john.fastabend, fancer.lancer,
	rmk+kernel, ahalaney, xiaolei.wang, rohan.g.thomas,
	Jianheng.Zhang, linux-kernel, linux-stm32, linux-arm-kernel, bpf,
	andrew, linux, horms, florian.fainelli, quic_abchauha

From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>

Introduce new variables plat_stmmacenet_data::snps_id,dev_id to allow glue
drivers to specify synopsys ID and device id respectively.
These values take precedence over reading from HW register. This facility
provides a mechansim to use setup function from stmmac core module and yet
override MAC.VERSION CSR if the glue driver chooses to do so.

Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
 include/linux/stmmac.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index d79ff252cfdc..4c4965a5a0d0 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -183,6 +183,8 @@ struct dwmac4_addrs {
 #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY	BIT(12)
 
 struct plat_stmmacenet_data {
+	u32 snps_id;
+	u32 dev_id;
 	int bus_id;
 	int phy_addr;
 	/* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 1/5] net: stmmac: Add snps_id, dev_id to struct plat_stmmacenet_data jitendra.vegiraju
@ 2024-10-18 20:53 ` jitendra.vegiraju
  2024-10-24  1:35   ` Abhishek Chauhan (ABC)
  2024-10-18 20:53 ` [PATCH net-next v6 3/5] net: stmmac: Integrate dw25gmac into stmmac hwif handling jitendra.vegiraju
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: jitendra.vegiraju @ 2024-10-18 20:53 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, jitendra.vegiraju, bcm-kernel-feedback-list,
	richardcochran, ast, daniel, hawk, john.fastabend, fancer.lancer,
	rmk+kernel, ahalaney, xiaolei.wang, rohan.g.thomas,
	Jianheng.Zhang, linux-kernel, linux-stm32, linux-arm-kernel, bpf,
	andrew, linux, horms, florian.fainelli, quic_abchauha

From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>

The BCM8958x uses early adopter version of DWC_xgmac version 4.00a for
Ethernet MAC. The DW25GMAC introduced in this version adds new DMA
architecture called Hyper-DMA (HDMA) for virtualization scalability.
This is realized by decoupling physical DMA channels(PDMA) from potentially
large number of virtual DMA channels (VDMA). The VDMAs are software
abstractions that map to PDMAs for frame transmission and reception.

Define new macros DW25GMAC_CORE_4_00 and DW25GMAC_ID to identify DW25GMAC
device.
To support the new HDMA architecture, a new instance of stmmac_dma_ops
dw25gmac400_dma_ops is added.
To support the current needs, a simple one-to-one mapping of dw25gmac's
logical VDMA (channel) to TC to PDMAs is used.
Most of the other dma operation functions in existing dwxgamc2_dma.c file
are reused where applicable.
Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core.

Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
 drivers/net/ethernet/stmicro/stmmac/Makefile  |   2 +-
 drivers/net/ethernet/stmicro/stmmac/common.h  |   4 +
 .../net/ethernet/stmicro/stmmac/dw25gmac.c    | 161 ++++++++++++++++++
 .../net/ethernet/stmicro/stmmac/dw25gmac.h    |  92 ++++++++++
 .../net/ethernet/stmicro/stmmac/dwxgmac2.h    |   1 +
 .../ethernet/stmicro/stmmac/dwxgmac2_core.c   |  42 +++++
 .../ethernet/stmicro/stmmac/dwxgmac2_dma.c    |  52 ++++++
 drivers/net/ethernet/stmicro/stmmac/hwif.h    |   1 +
 8 files changed, 354 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h

diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index c2f0e91f6bf8..967e8a9aa432 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\
 	      mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o	\
 	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
 	      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
-	      stmmac_xdp.o stmmac_est.o \
+	      stmmac_xdp.o stmmac_est.o dw25gmac.o \
 	      $(stmmac-y)
 
 stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 684489156dce..9a747b89ba51 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -38,9 +38,11 @@
 #define DWXGMAC_CORE_2_10	0x21
 #define DWXGMAC_CORE_2_20	0x22
 #define DWXLGMAC_CORE_2_00	0x20
+#define DW25GMAC_CORE_4_00	0x40
 
 /* Device ID */
 #define DWXGMAC_ID		0x76
+#define DW25GMAC_ID		0x55
 #define DWXLGMAC_ID		0x27
 
 #define STMMAC_CHAN0	0	/* Always supported and default for all chips */
@@ -563,6 +565,7 @@ struct mac_link {
 		u32 speed2500;
 		u32 speed5000;
 		u32 speed10000;
+		u32 speed25000;
 	} xgmii;
 	struct {
 		u32 speed25000;
@@ -621,6 +624,7 @@ int dwmac100_setup(struct stmmac_priv *priv);
 int dwmac1000_setup(struct stmmac_priv *priv);
 int dwmac4_setup(struct stmmac_priv *priv);
 int dwxgmac2_setup(struct stmmac_priv *priv);
+int dw25gmac_setup(struct stmmac_priv *priv);
 int dwxlgmac2_setup(struct stmmac_priv *priv);
 
 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
new file mode 100644
index 000000000000..8d0b45a7607a
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 Broadcom Corporation
+ */
+#include "stmmac.h"
+#include "dwxgmac2.h"
+#include "dw25gmac.h"
+
+u32 dw25gmac_decode_vdma_count(u32 regval)
+{
+	/* compressed encoding for vdma count */
+	if (regval < 16) /* Direct mapping */
+		return regval + 1;
+	else if (regval < 20) /* 20, 24, 28, 32 */
+		return 20 + (regval - 16) * 4;
+	else if (regval < 24) /* 40, 48, 56, 64 */
+		return 40 + (regval - 20) * 8;
+	else if (regval < 28) /* 80, 96, 112, 128 */
+		return 80 + (regval - 24) * 16;
+	else  /* not defined */
+		return 0;
+}
+
+static int rd_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel)
+{
+	u32 reg_val = 0;
+
+	reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
+	reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
+	reg_val |= XXVGMAC_CMD_TYPE | XXVGMAC_OB;
+	writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
+	return readl(ioaddr + XXVGMAC_DMA_CH_IND_DATA);
+}
+
+static void wr_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel, u32 val)
+{
+	u32 reg_val = 0;
+
+	writel(val, ioaddr + XXVGMAC_DMA_CH_IND_DATA);
+	reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
+	reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
+	reg_val |= XGMAC_OB;
+	writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
+}
+
+void dw25gmac_dma_init(void __iomem *ioaddr,
+		       struct stmmac_dma_cfg *dma_cfg)
+{
+	u32 tx_pdmas, rx_pdmas;
+	u32 hw_cap;
+	u32 value;
+	u32 i;
+
+	value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
+	value &= ~(XGMAC_AAL | XGMAC_EAME);
+	if (dma_cfg->aal)
+		value |= XGMAC_AAL;
+	if (dma_cfg->eame)
+		value |= XGMAC_EAME;
+	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
+
+	/* Get PDMA counts from HW */
+	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
+	tx_pdmas = FIELD_GET(XGMAC_HWFEAT_TXQCNT, hw_cap) + 1;
+	rx_pdmas = FIELD_GET(XGMAC_HWFEAT_RXQCNT, hw_cap) + 1;
+
+	/* Intialize all PDMAs with burst length fields */
+	for (i = 0; i < tx_pdmas; i++) {
+		value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i);
+		value &= ~(XXVGMAC_TXPBL | XXVGMAC_TPBLX8_MODE);
+		if (dma_cfg->pblx8)
+			value |= XXVGMAC_TPBLX8_MODE;
+		value |= FIELD_PREP(XXVGMAC_TXPBL, dma_cfg->pbl);
+		wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i, value);
+	}
+
+	for (i = 0; i < rx_pdmas; i++) {
+		value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i);
+		value &= ~(XXVGMAC_RXPBL | XXVGMAC_RPBLX8_MODE);
+		if (dma_cfg->pblx8)
+			value |= XXVGMAC_RPBLX8_MODE;
+		value |= FIELD_PREP(XXVGMAC_RXPBL, dma_cfg->pbl);
+		wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i, value);
+	}
+}
+
+void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
+			       void __iomem *ioaddr,
+			       struct stmmac_dma_cfg *dma_cfg,
+			       dma_addr_t dma_addr, u32 chan)
+{
+	u32 value;
+	u32 tc;
+
+	/* Descriptor cache size and prefetch threshold size */
+	value = rd_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan);
+	value &= ~XXVGMAC_TXDCSZ;
+	value |= FIELD_PREP(XXVGMAC_TXDCSZ,
+			    XXVGMAC_TXDCSZ_256BYTES);
+	value &= ~XXVGMAC_TDPS;
+	value |= FIELD_PREP(XXVGMAC_TDPS, XXVGMAC_TDPS_HALF);
+	wr_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan, value);
+
+	/* Use one-to-one mapping between VDMA, TC, and PDMA. */
+	tc = chan;
+
+	/* 1-to-1 PDMA to TC mapping */
+	value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan);
+	value &= ~XXVGMAC_TP2TCMP;
+	value |= FIELD_PREP(XXVGMAC_TP2TCMP, tc);
+	wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan, value);
+
+	/* 1-to-1 VDMA to TC mapping */
+	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
+	value &= ~XXVGMAC_TVDMA2TCMP;
+	value |= FIELD_PREP(XXVGMAC_TVDMA2TCMP, tc);
+	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
+
+	writel(upper_32_bits(dma_addr),
+	       ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
+	writel(lower_32_bits(dma_addr),
+	       ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
+}
+
+void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
+			       void __iomem *ioaddr,
+			       struct stmmac_dma_cfg *dma_cfg,
+			       dma_addr_t dma_addr, u32 chan)
+{
+	u32 value;
+	u32 tc;
+
+	/* Descriptor cache size and prefetch threshold size */
+	value = rd_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan);
+	value &= ~XXVGMAC_RXDCSZ;
+	value |= FIELD_PREP(XXVGMAC_RXDCSZ,
+			    XXVGMAC_RXDCSZ_256BYTES);
+	value &= ~XXVGMAC_RDPS;
+	value |= FIELD_PREP(XXVGMAC_RDPS, XXVGMAC_RDPS_HALF);
+	wr_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan, value);
+
+	/* Use one-to-one mapping between VDMA, TC, and PDMA. */
+	tc = chan;
+
+	/* 1-to-1 PDMA to TC mapping */
+	value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan);
+	value &= ~XXVGMAC_RP2TCMP;
+	value |= FIELD_PREP(XXVGMAC_RP2TCMP, tc);
+	wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan, value);
+
+	/* 1-to-1 VDMA to TC mapping */
+	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
+	value &= ~XXVGMAC_RVDMA2TCMP;
+	value |= FIELD_PREP(XXVGMAC_RVDMA2TCMP, tc);
+	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
+
+	writel(upper_32_bits(dma_addr),
+	       ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
+	writel(lower_32_bits(dma_addr),
+	       ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
+}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
new file mode 100644
index 000000000000..44f9601331d5
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2024 Broadcom Corporation
+ * DW25GMAC definitions.
+ */
+#ifndef __STMMAC_DW25GMAC_H__
+#define __STMMAC_DW25GMAC_H__
+
+/* Hardware features */
+#define XXVGMAC_HWFEAT_VDMA_RXCNT	GENMASK(16, 12)
+#define XXVGMAC_HWFEAT_VDMA_TXCNT	GENMASK(22, 18)
+
+/* DMA Indirect Registers*/
+#define XXVGMAC_DMA_CH_IND_CONTROL	0x00003080
+#define XXVGMAC_MODE_SELECT		GENMASK(27, 24)
+enum dma_ch_ind_modes {
+	MODE_TXEXTCFG	 = 0x0,	  /* Tx Extended Config */
+	MODE_RXEXTCFG	 = 0x1,	  /* Rx Extended Config */
+	MODE_TXDBGSTS	 = 0x2,	  /* Tx Debug Status */
+	MODE_RXDBGSTS	 = 0x3,	  /* Rx Debug Status */
+	MODE_TXDESCCTRL	 = 0x4,	  /* Tx Descriptor control */
+	MODE_RXDESCCTRL	 = 0x5,	  /* Rx Descriptor control */
+};
+
+#define XXVGMAC_ADDR_OFFSET		GENMASK(14, 8)
+#define XXVGMAC_AUTO_INCR		GENMASK(5, 4)
+#define XXVGMAC_CMD_TYPE		BIT(1)
+#define XXVGMAC_OB			BIT(0)
+#define XXVGMAC_DMA_CH_IND_DATA		0x00003084
+
+/* TX Config definitions */
+#define XXVGMAC_TXPBL			GENMASK(29, 24)
+#define XXVGMAC_TPBLX8_MODE		BIT(19)
+#define XXVGMAC_TP2TCMP			GENMASK(18, 16)
+#define XXVGMAC_ORRQ			GENMASK(13, 8)
+
+/* RX Config definitions */
+#define XXVGMAC_RXPBL			GENMASK(29, 24)
+#define XXVGMAC_RPBLX8_MODE		BIT(19)
+#define XXVGMAC_RP2TCMP			GENMASK(18, 16)
+#define XXVGMAC_OWRQ			GENMASK(13, 8)
+
+/* Tx Descriptor control */
+#define XXVGMAC_TXDCSZ			GENMASK(2, 0)
+#define XXVGMAC_TXDCSZ_0BYTES		0
+#define XXVGMAC_TXDCSZ_64BYTES		1
+#define XXVGMAC_TXDCSZ_128BYTES		2
+#define XXVGMAC_TXDCSZ_256BYTES		3
+#define XXVGMAC_TDPS			GENMASK(5, 3)
+#define XXVGMAC_TDPS_ZERO		0
+#define XXVGMAC_TDPS_1_8TH		1
+#define XXVGMAC_TDPS_1_4TH		2
+#define XXVGMAC_TDPS_HALF		3
+#define XXVGMAC_TDPS_3_4TH		4
+
+/* Rx Descriptor control */
+#define XXVGMAC_RXDCSZ			GENMASK(2, 0)
+#define XXVGMAC_RXDCSZ_0BYTES		0
+#define XXVGMAC_RXDCSZ_64BYTES		1
+#define XXVGMAC_RXDCSZ_128BYTES		2
+#define XXVGMAC_RXDCSZ_256BYTES		3
+#define XXVGMAC_RDPS			GENMASK(5, 3)
+#define XXVGMAC_RDPS_ZERO		0
+#define XXVGMAC_RDPS_1_8TH		1
+#define XXVGMAC_RDPS_1_4TH		2
+#define XXVGMAC_RDPS_HALF		3
+#define XXVGMAC_RDPS_3_4TH		4
+
+/* DWCXG_DMA_CH(#i) Registers*/
+#define XXVGMAC_DSL			GENMASK(20, 18)
+#define XXVGMAC_MSS			GENMASK(13, 0)
+#define XXVGMAC_TFSEL			GENMASK(30, 29)
+#define XXVGMAC_TQOS			GENMASK(27, 24)
+#define XXVGMAC_IPBL			BIT(15)
+#define XXVGMAC_TVDMA2TCMP		GENMASK(6, 4)
+#define XXVGMAC_RPF			BIT(31)
+#define XXVGMAC_RVDMA2TCMP		GENMASK(30, 28)
+#define XXVGMAC_RQOS			GENMASK(27, 24)
+
+u32 dw25gmac_decode_vdma_count(u32 regval);
+
+void dw25gmac_dma_init(void __iomem *ioaddr,
+		       struct stmmac_dma_cfg *dma_cfg);
+
+void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
+			       void __iomem *ioaddr,
+			       struct stmmac_dma_cfg *dma_cfg,
+			       dma_addr_t dma_addr, u32 chan);
+void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
+			       void __iomem *ioaddr,
+			       struct stmmac_dma_cfg *dma_cfg,
+			       dma_addr_t dma_addr, u32 chan);
+#endif /* __STMMAC_DW25GMAC_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 6a2c7d22df1e..c9424c5a6ce5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -17,6 +17,7 @@
 #define XGMAC_CONFIG_SS_OFF		29
 #define XGMAC_CONFIG_SS_MASK		GENMASK(31, 29)
 #define XGMAC_CONFIG_SS_10000		(0x0 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_25000		(0x1 << XGMAC_CONFIG_SS_OFF)
 #define XGMAC_CONFIG_SS_2500_GMII	(0x2 << XGMAC_CONFIG_SS_OFF)
 #define XGMAC_CONFIG_SS_1000_GMII	(0x3 << XGMAC_CONFIG_SS_OFF)
 #define XGMAC_CONFIG_SS_100_MII		(0x4 << XGMAC_CONFIG_SS_OFF)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index f519d43738b0..96013b489af6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -11,6 +11,7 @@
 #include "stmmac_ptp.h"
 #include "dwxlgmac2.h"
 #include "dwxgmac2.h"
+#include "dw25gmac.h"
 
 static void dwxgmac2_core_init(struct mac_device_info *hw,
 			       struct net_device *dev)
@@ -1670,6 +1671,47 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
 	return 0;
 }
 
+int dw25gmac_setup(struct stmmac_priv *priv)
+{
+	struct mac_device_info *mac = priv->hw;
+
+	dev_info(priv->device, "\tDW25GMAC\n");
+
+	priv->dev->priv_flags |= IFF_UNICAST_FLT;
+	mac->pcsr = priv->ioaddr;
+	mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
+	mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
+	mac->mcast_bits_log2 = 0;
+
+	if (mac->multicast_filter_bins)
+		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
+
+	mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+			 MAC_1000FD | MAC_2500FD | MAC_5000FD |
+			 MAC_10000FD | MAC_25000FD;
+	mac->link.duplex = 0;
+	mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
+	mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
+	mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
+	mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
+	mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
+	mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
+	mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
+	mac->link.xgmii.speed25000 = XGMAC_CONFIG_SS_25000;
+	mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
+
+	mac->mii.addr = XGMAC_MDIO_ADDR;
+	mac->mii.data = XGMAC_MDIO_DATA;
+	mac->mii.addr_shift = 16;
+	mac->mii.addr_mask = GENMASK(20, 16);
+	mac->mii.reg_shift = 0;
+	mac->mii.reg_mask = GENMASK(15, 0);
+	mac->mii.clk_csr_shift = 19;
+	mac->mii.clk_csr_mask = GENMASK(21, 19);
+
+	return 0;
+}
+
 int dwxlgmac2_setup(struct stmmac_priv *priv)
 {
 	struct mac_device_info *mac = priv->hw;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 7840bc403788..2e86eaafd16e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -7,6 +7,7 @@
 #include <linux/iopoll.h>
 #include "stmmac.h"
 #include "dwxgmac2.h"
+#include "dw25gmac.h"
 
 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
 {
@@ -500,6 +501,27 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
 	return 0;
 }
 
+static int dw25gmac_get_hw_feature(void __iomem *ioaddr,
+				   struct dma_features *dma_cap)
+
+{
+	u32 hw_cap;
+	int ret;
+
+	ret = dwxgmac2_get_hw_feature(ioaddr, dma_cap);
+
+	/* For DW25GMAC VDMA channel count is channel count */
+	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
+	dma_cap->number_tx_channel =
+		dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_TXCNT,
+					    hw_cap));
+	dma_cap->number_rx_channel =
+		dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_RXCNT,
+					    hw_cap));
+
+	return ret;
+}
+
 static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
 				 u32 riwt, u32 queue)
 {
@@ -641,3 +663,33 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = {
 	.enable_sph = dwxgmac2_enable_sph,
 	.enable_tbs = dwxgmac2_enable_tbs,
 };
+
+const struct stmmac_dma_ops dw25gmac400_dma_ops = {
+	.reset = dwxgmac2_dma_reset,
+	.init = dw25gmac_dma_init,
+	.init_chan = dwxgmac2_dma_init_chan,
+	.init_rx_chan = dw25gmac_dma_init_rx_chan,
+	.init_tx_chan = dw25gmac_dma_init_tx_chan,
+	.axi = dwxgmac2_dma_axi,
+	.dump_regs = dwxgmac2_dma_dump_regs,
+	.dma_rx_mode = dwxgmac2_dma_rx_mode,
+	.dma_tx_mode = dwxgmac2_dma_tx_mode,
+	.enable_dma_irq = dwxgmac2_enable_dma_irq,
+	.disable_dma_irq = dwxgmac2_disable_dma_irq,
+	.start_tx = dwxgmac2_dma_start_tx,
+	.stop_tx = dwxgmac2_dma_stop_tx,
+	.start_rx = dwxgmac2_dma_start_rx,
+	.stop_rx = dwxgmac2_dma_stop_rx,
+	.dma_interrupt = dwxgmac2_dma_interrupt,
+	.get_hw_feature = dw25gmac_get_hw_feature,
+	.rx_watchdog = dwxgmac2_rx_watchdog,
+	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
+	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
+	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
+	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
+	.enable_tso = dwxgmac2_enable_tso,
+	.qmode = dwxgmac2_qmode,
+	.set_bfsize = dwxgmac2_set_bfsize,
+	.enable_sph = dwxgmac2_enable_sph,
+	.enable_tbs = dwxgmac2_enable_tbs,
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index d5a9f01ecac5..774ea8cd5ae9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -702,6 +702,7 @@ extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
 extern const struct stmmac_mmc_ops dwmac_mmc_ops;
 extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;
 extern const struct stmmac_est_ops dwmac510_est_ops;
+extern const struct stmmac_dma_ops dw25gmac400_dma_ops;
 
 #define GMAC_VERSION		0x00000020	/* GMAC CORE Version */
 #define GMAC4_VERSION		0x00000110	/* GMAC4+ CORE Version */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH net-next v6 3/5] net: stmmac: Integrate dw25gmac into stmmac hwif handling
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 1/5] net: stmmac: Add snps_id, dev_id to struct plat_stmmacenet_data jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core jitendra.vegiraju
@ 2024-10-18 20:53 ` jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 4/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 19+ messages in thread
From: jitendra.vegiraju @ 2024-10-18 20:53 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, jitendra.vegiraju, bcm-kernel-feedback-list,
	richardcochran, ast, daniel, hawk, john.fastabend, fancer.lancer,
	rmk+kernel, ahalaney, xiaolei.wang, rohan.g.thomas,
	Jianheng.Zhang, linux-kernel, linux-stm32, linux-arm-kernel, bpf,
	andrew, linux, horms, florian.fainelli, quic_abchauha

From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>

Integrate dw25gmac support into stmmac hardware interface handling.
Added a new entry to the stmmac_hw table in hwif.c.
Since BCM8958x is an early adopter device, the synopsis_id reported in HW
is 0x32 and device_id is DWXGMAC_ID. Provide override support by giving
preference to snps_id, dev_id values when initialized to non-zero
values by glue driver.

Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
 drivers/net/ethernet/stmicro/stmmac/hwif.c | 26 +++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 88cce28b2f98..b8ee7bf20037 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -257,6 +257,27 @@ static const struct stmmac_hwif_entry {
 		.est = &dwmac510_est_ops,
 		.setup = dwxgmac2_setup,
 		.quirks = NULL,
+	}, {
+		.gmac = false,
+		.gmac4 = false,
+		.xgmac = true,
+		.min_id = DW25GMAC_CORE_4_00,
+		.dev_id = DW25GMAC_ID,
+		.regs = {
+			.ptp_off = PTP_XGMAC_OFFSET,
+			.mmc_off = MMC_XGMAC_OFFSET,
+			.est_off = EST_XGMAC_OFFSET,
+		},
+		.desc = &dwxgmac210_desc_ops,
+		.dma = &dw25gmac400_dma_ops,
+		.mac = &dwxgmac210_ops,
+		.hwtimestamp = &stmmac_ptp,
+		.mode = NULL,
+		.tc = &dwmac510_tc_ops,
+		.mmc = &dwxgmac_mmc_ops,
+		.est = &dwmac510_est_ops,
+		.setup = dw25gmac_setup,
+		.quirks = NULL,
 	}, {
 		.gmac = false,
 		.gmac4 = false,
@@ -292,7 +313,10 @@ int stmmac_hwif_init(struct stmmac_priv *priv)
 	u32 id, dev_id = 0;
 	int i, ret;
 
-	if (needs_gmac) {
+	if (priv->plat->snps_id && priv->plat->dev_id) {
+		id = priv->plat->snps_id;
+		dev_id = priv->plat->dev_id;
+	} else if (needs_gmac) {
 		id = stmmac_get_id(priv, GMAC_VERSION);
 	} else if (needs_gmac4 || needs_xgmac) {
 		id = stmmac_get_id(priv, GMAC4_VERSION);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH net-next v6 4/5] net: stmmac: Add PCI driver support for BCM8958x
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
                   ` (2 preceding siblings ...)
  2024-10-18 20:53 ` [PATCH net-next v6 3/5] net: stmmac: Integrate dw25gmac into stmmac hwif handling jitendra.vegiraju
@ 2024-10-18 20:53 ` jitendra.vegiraju
  2024-10-18 20:53 ` [PATCH net-next v6 5/5] net: stmmac: Add BCM8958x driver to build system jitendra.vegiraju
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 19+ messages in thread
From: jitendra.vegiraju @ 2024-10-18 20:53 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, jitendra.vegiraju, bcm-kernel-feedback-list,
	richardcochran, ast, daniel, hawk, john.fastabend, fancer.lancer,
	rmk+kernel, ahalaney, xiaolei.wang, rohan.g.thomas,
	Jianheng.Zhang, linux-kernel, linux-stm32, linux-arm-kernel, bpf,
	andrew, linux, horms, florian.fainelli, quic_abchauha

From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>

Add PCI ethernet driver support for Broadcom BCM8958x SoC devices used
in automotive applications.

This SoC device has PCIe ethernet MAC attached to an integrated ethernet
switch using XGMII interface. The PCIe ethernet controller is presented to
the Linux host as PCI network device.

The following block diagram gives an overview of the application.
             +=================================+
             |       Host CPU/Linux            |
             +=================================+
                        || PCIe
                        ||
        +==========================================+
        |           +--------------+               |
        |           | PCIE Endpoint|               |
        |           | Ethernet     |               |
        |           | Controller   |               |
        |           |   DMA        |               |
        |           +--------------+               |
        |           |   MAC        |   BCM8958X    |
        |           +--------------+   SoC         |
        |               || XGMII                   |
        |               ||                         |
        |           +--------------+               |
        |           | Ethernet     |               |
        |           | switch       |               |
        |           +--------------+               |
        |             || || || ||                  |
        +==========================================+
                      || || || || More external interfaces

The MAC IP block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
driver uses common dwxgmac2 code where applicable.
Driver functionality specific to this MAC is implemented in dw25gmac.c.

Management of integrated ethernet switch on this SoC is not handled by
the PCIe interface.
Since BCM8958x is an early adopter device, override the hardware reported
synopsis versions with actual DW25MAC versions that support hdma.

This SoC device has PCIe ethernet MAC directly attached to an integrated
ethernet switch using XGMII interface. Since device tree support is not
available on this platform, a software node is created to enable
fixed-link support using phylink driver.

Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-brcm.c  | 478 ++++++++++++++++++
 .../net/ethernet/stmicro/stmmac/stmmac_main.c |  26 +
 2 files changed, 504 insertions(+)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
new file mode 100644
index 000000000000..d245af503fe8
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2024 Broadcom Corporation
+ *
+ * PCI driver for ethernet interface of BCM8958X automotive switch chip.
+ *
+ * High level block diagram of the device.
+ *              +=================================+
+ *              |       Host CPU/Linux            |
+ *              +=================================+
+ *                         || PCIe
+ *                         ||
+ *         +==========================================+
+ *         |           +--------------+               |
+ *         |           | PCIE Endpoint|               |
+ *         |           | Ethernet     |               |
+ *         |           | Controller   |               |
+ *         |           |   DMA        |               |
+ *         |           +--------------+               |
+ *         |           |   MAC        |   BCM8958X    |
+ *         |           +--------------+   SoC         |
+ *         |               || XGMII                   |
+ *         |               ||                         |
+ *         |           +--------------+               |
+ *         |           | Ethernet     |               |
+ *         |           | switch       |               |
+ *         |           +--------------+               |
+ *         |             || || || ||                  |
+ *         +==========================================+
+ *                       || || || || More external interfaces
+ *
+ * This SoC device has PCIe ethernet MAC directly attached to an integrated
+ * ethernet switch using XGMII interface. Since devicetree support is not
+ * available on this platform, a software node is created to enable
+ * fixed-link support using phylink driver.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/dmi.h>
+#include <linux/pci.h>
+#include <linux/phy.h>
+
+#include "stmmac.h"
+#include "dwxgmac2.h"
+#include "dw25gmac.h"
+
+#define PCI_DEVICE_ID_BROADCOM_BCM8958X		0xa00d
+#define BRCM_MAX_MTU				1500
+
+/* TX and RX Queue counts */
+#define BRCM_TX_Q_COUNT				4
+#define BRCM_RX_Q_COUNT				4
+
+#define BRCM_XGMAC_BAR0_MASK			BIT(0)
+
+#define BRCM_XGMAC_IOMEM_MISC_REG_OFFSET	0x0
+#define BRCM_XGMAC_IOMEM_MBOX_REG_OFFSET	0x1000
+#define BRCM_XGMAC_IOMEM_CFG_REG_OFFSET		0x3000
+
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW	0x940
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE	0x00000001
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH	0x944
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE	0x88000000
+
+#define XGMAC_PCIE_MISC_MII_CTRL_OFFSET			0x4
+#define XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX		BIT(0)
+#define XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX		BIT(1)
+#define XGMAC_PCIE_MISC_MII_CTRL_LINK_UP		BIT(2)
+#define XGMAC_PCIE_MISC_PCIESS_CTRL_OFFSET		0x8
+#define XGMAC_PCIE_MISC_PCIESS_CTRL_EN_MSI_MSIX		BIT(9)
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET	0x90
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE	0x00000001
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET	0x94
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE	0x88000000
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_OFFSET	0x700
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_VALUE	1
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_OFFSET	0x704
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_VALUE	1
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_OFFSET	0x728
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_VALUE	1
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_OFFSET	0x740
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_VALUE	0
+
+/* MSIX Vector map register starting offsets */
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_RX0_PF0_OFFSET	0x840
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_TX0_PF0_OFFSET	0x890
+#define BRCM_MAX_DMA_CHANNEL_PAIRS		4
+#define BRCM_XGMAC_MSI_MAC_VECTOR		0
+#define BRCM_XGMAC_MSI_RX_VECTOR_START		1
+#define BRCM_XGMAC_MSI_TX_VECTOR_START		2
+#define BRCM_XGMAC_MSI_VECTOR_MAX	(BRCM_XGMAC_MSI_RX_VECTOR_START + \
+					 BRCM_MAX_DMA_CHANNEL_PAIRS * 2)
+
+static char *fixed_link_node_name = "fixed-link";
+
+static const struct property_entry fixed_link_properties[] = {
+	PROPERTY_ENTRY_U32("speed", 10000),
+	PROPERTY_ENTRY_BOOL("full-duplex"),
+	PROPERTY_ENTRY_BOOL("pause"),
+	{ }
+};
+
+struct brcm_priv_data {
+	void __iomem *mbox_regs;    /* MBOX  Registers*/
+	void __iomem *misc_regs;    /* MISC  Registers*/
+	void __iomem *xgmac_regs;   /* XGMAC Registers*/
+	struct software_node fixed_link_node;
+};
+
+struct dwxgmac_brcm_pci_info {
+	int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
+};
+
+static void misc_iowrite(struct brcm_priv_data *brcm_priv,
+			 u32 reg, u32 val)
+{
+	iowrite32(val, brcm_priv->misc_regs + reg);
+}
+
+static void dwxgmac_brcm_common_default_data(struct plat_stmmacenet_data *plat)
+{
+	int i;
+
+	plat->has_xgmac = 1;
+	plat->force_sf_dma_mode = 1;
+	plat->mac_port_sel_speed = SPEED_10000;
+	plat->clk_ptp_rate = 125000000;
+	plat->clk_ref_rate = 250000000;
+	plat->tx_coe = 1;
+	plat->rx_coe = 1;
+	plat->max_speed = SPEED_10000;
+
+	/* Set default value for multicast hash bins */
+	plat->multicast_filter_bins = HASH_TABLE_SIZE;
+
+	/* Set default value for unicast filter entries */
+	plat->unicast_filter_entries = 1;
+
+	/* Set the maxmtu to device's default */
+	plat->maxmtu = BRCM_MAX_MTU;
+
+	/* Set default number of RX and TX queues to use */
+	plat->tx_queues_to_use = BRCM_TX_Q_COUNT;
+	plat->rx_queues_to_use = BRCM_RX_Q_COUNT;
+
+	plat->tx_sched_algorithm = MTL_TX_ALGORITHM_SP;
+	for (i = 0; i < plat->tx_queues_to_use; i++) {
+		plat->tx_queues_cfg[i].use_prio = false;
+		plat->tx_queues_cfg[i].prio = 0;
+		plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_AVB;
+	}
+
+	plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
+	for (i = 0; i < plat->rx_queues_to_use; i++) {
+		plat->rx_queues_cfg[i].use_prio = false;
+		plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_AVB;
+		plat->rx_queues_cfg[i].pkt_route = 0x0;
+		plat->rx_queues_cfg[i].chan = i;
+	}
+}
+
+static int dwxgmac_brcm_default_data(struct pci_dev *pdev,
+				     struct plat_stmmacenet_data *plat)
+{
+	/* Set common default data first */
+	dwxgmac_brcm_common_default_data(plat);
+
+	plat->snps_id = DW25GMAC_CORE_4_00;
+	plat->dev_id = DW25GMAC_ID;
+	plat->bus_id = 0;
+	plat->phy_addr = 0;
+	plat->phy_interface = PHY_INTERFACE_MODE_XGMII;
+
+	plat->dma_cfg->pbl = 32;
+	plat->dma_cfg->pblx8 = 0;
+	plat->dma_cfg->aal = 0;
+	plat->dma_cfg->eame = 1;
+
+	plat->axi->axi_wr_osr_lmt = 31;
+	plat->axi->axi_rd_osr_lmt = 31;
+	plat->axi->axi_fb = 0;
+	plat->axi->axi_blen[0] = 4;
+	plat->axi->axi_blen[1] = 8;
+	plat->axi->axi_blen[2] = 16;
+	plat->axi->axi_blen[3] = 32;
+	plat->axi->axi_blen[4] = 64;
+	plat->axi->axi_blen[5] = 128;
+	plat->axi->axi_blen[6] = 256;
+
+	return 0;
+}
+
+static struct dwxgmac_brcm_pci_info dwxgmac_brcm_pci_info = {
+	.setup = dwxgmac_brcm_default_data,
+};
+
+static void brcm_config_misc_regs(struct pci_dev *pdev,
+				  struct brcm_priv_data *brcm_priv)
+{
+	pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW,
+			       XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE);
+	pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH,
+			       XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE);
+
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE);
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE);
+
+	/* Enable Switch Link */
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MII_CTRL_OFFSET,
+		     XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX |
+		     XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX |
+		     XGMAC_PCIE_MISC_MII_CTRL_LINK_UP);
+}
+
+static int brcm_config_multi_msi(struct pci_dev *pdev,
+				 struct plat_stmmacenet_data *plat,
+				 struct stmmac_resources *res)
+{
+	int ret;
+	int i;
+
+	ret = pci_alloc_irq_vectors(pdev, BRCM_XGMAC_MSI_VECTOR_MAX,
+				    BRCM_XGMAC_MSI_VECTOR_MAX,
+				    PCI_IRQ_MSI | PCI_IRQ_MSIX);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "%s: multi MSI enablement failed\n",
+			__func__);
+		return ret;
+	}
+
+	/* For RX MSI */
+	for (i = 0; i < plat->rx_queues_to_use; i++)
+		res->rx_irq[i] =
+			pci_irq_vector(pdev,
+				       BRCM_XGMAC_MSI_RX_VECTOR_START + i * 2);
+
+	/* For TX MSI */
+	for (i = 0; i < plat->tx_queues_to_use; i++)
+		res->tx_irq[i] =
+			pci_irq_vector(pdev,
+				       BRCM_XGMAC_MSI_TX_VECTOR_START + i * 2);
+
+	res->irq = pci_irq_vector(pdev, BRCM_XGMAC_MSI_MAC_VECTOR);
+
+	plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
+	plat->flags |= STMMAC_FLAG_TSO_EN;
+
+	return 0;
+}
+
+static int dwxgmac_brcm_pci_probe(struct pci_dev *pdev,
+				  const struct pci_device_id *id)
+{
+	struct dwxgmac_brcm_pci_info *info =
+		(struct dwxgmac_brcm_pci_info *)id->driver_data;
+	struct plat_stmmacenet_data *plat;
+	struct brcm_priv_data *brcm_priv;
+	struct stmmac_resources res;
+	struct device *dev;
+	int rx_offset;
+	int tx_offset;
+	int vector;
+	int ret;
+
+	dev = &pdev->dev;
+
+	brcm_priv = devm_kzalloc(&pdev->dev, sizeof(*brcm_priv), GFP_KERNEL);
+	if (!brcm_priv)
+		return -ENOMEM;
+
+	plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
+	if (!plat)
+		return -ENOMEM;
+
+	plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
+				     GFP_KERNEL);
+	if (!plat->dma_cfg)
+		return -ENOMEM;
+
+	plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
+	if (!plat->axi)
+		return -ENOMEM;
+
+	/* This device is directly attached to the switch chip internal to the
+	 * SoC using XGMII interface. Since no MDIO is present, register
+	 * fixed-link software_node to create phylink.
+	 */
+	plat->port_node = fwnode_create_software_node(NULL, NULL);
+	brcm_priv->fixed_link_node.name = fixed_link_node_name;
+	brcm_priv->fixed_link_node.properties = fixed_link_properties;
+	brcm_priv->fixed_link_node.parent = to_software_node(plat->port_node);
+	device_add_software_node(dev, &brcm_priv->fixed_link_node);
+
+	/* Disable D3COLD as our device does not support it */
+	pci_d3cold_disable(pdev);
+
+	/* Enable PCI device */
+	ret = pcim_enable_device(pdev);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
+			__func__);
+		return ret;
+	}
+
+	/* Get the base address of device */
+	ret = pcim_iomap_regions(pdev, BRCM_XGMAC_BAR0_MASK, pci_name(pdev));
+	if (ret)
+		return ret;
+	pci_set_master(pdev);
+
+	memset(&res, 0, sizeof(res));
+	res.addr = pcim_iomap_table(pdev)[0];
+	/* MISC Regs */
+	brcm_priv->misc_regs = res.addr + BRCM_XGMAC_IOMEM_MISC_REG_OFFSET;
+	/* MBOX Regs */
+	brcm_priv->mbox_regs = res.addr + BRCM_XGMAC_IOMEM_MBOX_REG_OFFSET;
+	/* XGMAC config Regs */
+	res.addr += BRCM_XGMAC_IOMEM_CFG_REG_OFFSET;
+	brcm_priv->xgmac_regs = res.addr;
+
+	plat->bsp_priv = brcm_priv;
+
+	ret = info->setup(pdev, plat);
+	if (ret)
+		return ret;
+
+	pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW,
+			       XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE);
+	pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH,
+			       XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE);
+
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE);
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE);
+
+	/* SBD Interrupt */
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_VALUE);
+	/* EP_DOORBELL Interrupt */
+	misc_iowrite(brcm_priv,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_VALUE);
+	/* EP_H0 Interrupt */
+	misc_iowrite(brcm_priv,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_VALUE);
+	/* EP_H1 Interrupt */
+	misc_iowrite(brcm_priv,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_OFFSET,
+		     XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_VALUE);
+
+	rx_offset = XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_RX0_PF0_OFFSET;
+	tx_offset = XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_TX0_PF0_OFFSET;
+	vector = BRCM_XGMAC_MSI_RX_VECTOR_START;
+	for (int i = 0; i < BRCM_MAX_DMA_CHANNEL_PAIRS; i++) {
+		/* RX Interrupt */
+		misc_iowrite(brcm_priv, rx_offset, vector++);
+		/* TX Interrupt */
+		misc_iowrite(brcm_priv, tx_offset, vector++);
+		rx_offset += 4;
+		tx_offset += 4;
+	}
+
+	/* Enable Switch Link */
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MII_CTRL_OFFSET,
+		     XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX |
+		     XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX |
+		     XGMAC_PCIE_MISC_MII_CTRL_LINK_UP);
+	/* Enable MSI-X */
+	misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_PCIESS_CTRL_OFFSET,
+		     XGMAC_PCIE_MISC_PCIESS_CTRL_EN_MSI_MSIX);
+
+	ret = brcm_config_multi_msi(pdev, plat, &res);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"%s: ERROR: failed to enable IRQ\n", __func__);
+		goto err_disable_msi;
+	}
+
+	ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
+	if (ret)
+		goto err_disable_msi;
+
+	return ret;
+
+err_disable_msi:
+	pci_free_irq_vectors(pdev);
+
+	return ret;
+}
+
+static void dwxgmac_brcm_software_node_remove(struct pci_dev *pdev)
+{
+	struct fwnode_handle *fwnode;
+	struct stmmac_priv *priv;
+	struct net_device *ndev;
+	struct device *dev;
+
+	dev = &pdev->dev;
+	ndev = dev_get_drvdata(dev);
+	priv = netdev_priv(ndev);
+	fwnode = priv->plat->port_node;
+
+	fwnode_remove_software_node(fwnode);
+	device_remove_software_node(dev);
+}
+
+static void dwxgmac_brcm_pci_remove(struct pci_dev *pdev)
+{
+	stmmac_dvr_remove(&pdev->dev);
+	pci_free_irq_vectors(pdev);
+	pcim_iounmap_regions(pdev, BRCM_XGMAC_BAR0_MASK);
+	pci_clear_master(pdev);
+	dwxgmac_brcm_software_node_remove(pdev);
+}
+
+static int __maybe_unused dwxgmac_brcm_pci_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	int ret;
+
+	ret = stmmac_suspend(dev);
+	if (ret)
+		return ret;
+
+	ret = pci_save_state(pdev);
+	if (ret)
+		return ret;
+
+	pci_disable_device(pdev);
+	pci_wake_from_d3(pdev, true);
+
+	return 0;
+}
+
+static int __maybe_unused dwxgmac_brcm_pci_resume(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct stmmac_priv *priv;
+	struct net_device *ndev;
+
+	ndev = dev_get_drvdata(dev);
+	priv = netdev_priv(ndev);
+	brcm_config_misc_regs(pdev, priv->plat->bsp_priv);
+
+	pci_restore_state(pdev);
+	pci_set_power_state(pdev, PCI_D0);
+
+	return stmmac_resume(dev);
+}
+
+static SIMPLE_DEV_PM_OPS(dwxgmac_brcm_pm_ops,
+			 dwxgmac_brcm_pci_suspend,
+			 dwxgmac_brcm_pci_resume);
+
+static const struct pci_device_id dwxgmac_brcm_id_table[] = {
+	{ PCI_DEVICE_DATA(BROADCOM, BCM8958X, &dwxgmac_brcm_pci_info) },
+	{}
+};
+
+MODULE_DEVICE_TABLE(pci, dwxgmac_brcm_id_table);
+
+static struct pci_driver dwxgmac_brcm_pci_driver = {
+	.name = "brcm-bcm8958x",
+	.id_table = dwxgmac_brcm_id_table,
+	.probe	= dwxgmac_brcm_pci_probe,
+	.remove = dwxgmac_brcm_pci_remove,
+	.driver = {
+		.pm = &dwxgmac_brcm_pm_ops,
+	},
+};
+
+module_pci_driver(dwxgmac_brcm_pci_driver);
+
+MODULE_DESCRIPTION("Broadcom 10G Automotive Ethernet PCIe driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index d3895d7eecfc..5b2ff7dbd47e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1040,6 +1040,32 @@ static void stmmac_mac_link_up(struct phylink_config *config,
 		default:
 			return;
 		}
+	} else if (interface == PHY_INTERFACE_MODE_XGMII) {
+		switch (speed) {
+		case SPEED_25000:
+			ctrl |= priv->hw->link.xgmii.speed25000;
+			break;
+		case SPEED_10000:
+			ctrl |= priv->hw->link.xgmii.speed10000;
+			break;
+		case SPEED_5000:
+			ctrl |= priv->hw->link.xgmii.speed5000;
+			break;
+		case SPEED_2500:
+			ctrl |= priv->hw->link.xgmii.speed2500;
+			break;
+		case SPEED_1000:
+			ctrl |= priv->hw->link.speed1000;
+			break;
+		case SPEED_100:
+			ctrl |= priv->hw->link.speed100;
+			break;
+		case SPEED_10:
+			ctrl |= priv->hw->link.speed10;
+			break;
+		default:
+			return;
+		}
 	} else if (interface == PHY_INTERFACE_MODE_XLGMII) {
 		switch (speed) {
 		case SPEED_100000:
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH net-next v6 5/5] net: stmmac: Add BCM8958x driver to build system
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
                   ` (3 preceding siblings ...)
  2024-10-18 20:53 ` [PATCH net-next v6 4/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
@ 2024-10-18 20:53 ` jitendra.vegiraju
  2024-10-21 11:05 ` [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x Serge Semin
  2024-11-05 16:12 ` Jitendra Vegiraju
  6 siblings, 0 replies; 19+ messages in thread
From: jitendra.vegiraju @ 2024-10-18 20:53 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, jitendra.vegiraju, bcm-kernel-feedback-list,
	richardcochran, ast, daniel, hawk, john.fastabend, fancer.lancer,
	rmk+kernel, ahalaney, xiaolei.wang, rohan.g.thomas,
	Jianheng.Zhang, linux-kernel, linux-stm32, linux-arm-kernel, bpf,
	andrew, linux, horms, florian.fainelli, quic_abchauha

From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>

Add PCI driver for BCM8958x to the linux build system and
update MAINTAINERS file.

Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
 MAINTAINERS                                  |  8 ++++++++
 drivers/net/ethernet/stmicro/stmmac/Kconfig  | 11 +++++++++++
 drivers/net/ethernet/stmicro/stmmac/Makefile |  1 +
 3 files changed, 20 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d678a58c0205..f5ded80446d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4464,6 +4464,14 @@ N:	brcmstb
 N:	bcm7038
 N:	bcm7120
 
+BROADCOM BCM8958X ETHERNET DRIVER
+M:	Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
+R:	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	drivers/net/ethernet/stmicro/stmmac/dw25gmac.*
+F:	drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
+
 BROADCOM BCMBCA ARM ARCHITECTURE
 M:	William Zhang <william.zhang@broadcom.com>
 M:	Anand Gore <anand.gore@broadcom.com>
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 05cc07b8f48c..47c9db123b03 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -298,6 +298,17 @@ config DWMAC_LOONGSON
 	  This selects the LOONGSON PCI bus support for the stmmac driver,
 	  Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bridge.
 
+config DWMAC_BRCM
+	tristate "Broadcom XGMAC support"
+	depends on STMMAC_ETH && PCI
+	depends on COMMON_CLK
+	help
+	  Support for ethernet controllers on Broadcom BCM8958x SoCs.
+
+	  This selects Broadcom XGMAC specific PCI bus support for the
+	  stmmac driver. This driver provides the glue layer on top of the
+	  stmmac driver required for the Broadcom BCM8958x SoC devices.
+
 config STMMAC_PCI
 	tristate "STMMAC PCI bus support"
 	depends on STMMAC_ETH && PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 967e8a9aa432..517981b9e93a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -41,4 +41,5 @@ dwmac-altr-socfpga-objs := dwmac-socfpga.o
 obj-$(CONFIG_STMMAC_PCI)	+= stmmac-pci.o
 obj-$(CONFIG_DWMAC_INTEL)	+= dwmac-intel.o
 obj-$(CONFIG_DWMAC_LOONGSON)	+= dwmac-loongson.o
+obj-$(CONFIG_DWMAC_BRCM)	+= dwmac-brcm.o
 stmmac-pci-objs:= stmmac_pci.o
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
                   ` (4 preceding siblings ...)
  2024-10-18 20:53 ` [PATCH net-next v6 5/5] net: stmmac: Add BCM8958x driver to build system jitendra.vegiraju
@ 2024-10-21 11:05 ` Serge Semin
  2024-10-21 16:01   ` Jitendra Vegiraju
  2024-11-05 16:12 ` Jitendra Vegiraju
  6 siblings, 1 reply; 19+ messages in thread
From: Serge Semin @ 2024-10-21 11:05 UTC (permalink / raw)
  To: jitendra.vegiraju
  Cc: netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, rmk+kernel, ahalaney, xiaolei.wang,
	rohan.g.thomas, Jianheng.Zhang, linux-kernel, linux-stm32,
	linux-arm-kernel, bpf, andrew, linux, horms, florian.fainelli,
	quic_abchauha

Hi Jitendra

On Fri, Oct 18, 2024 at 01:53:27PM GMT, jitendra.vegiraju@broadcom.com wrote:
> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
> 
> This patchset adds basic PCI ethernet device driver support for Broadcom
> BCM8958x Automotive Ethernet switch SoC devices.
> 
> This SoC device has PCIe ethernet MAC attached to an integrated ethernet
> switch using XGMII interface. The PCIe ethernet controller is presented to
> the Linux host as PCI network device.
> 
> The following block diagram gives an overview of the application.
>              +=================================+
>              |       Host CPU/Linux            |
>              +=================================+
>                         || PCIe
>                         ||
>         +==========================================+
>         |           +--------------+               |
>         |           | PCIE Endpoint|               |
>         |           | Ethernet     |               |
>         |           | Controller   |               |
>         |           |   DMA        |               |
>         |           +--------------+               |
>         |           |   MAC        |   BCM8958X    |
>         |           +--------------+   SoC         |
>         |               || XGMII                   |
>         |               ||                         |
>         |           +--------------+               |
>         |           | Ethernet     |               |
>         |           | switch       |               |
>         |           +--------------+               |
>         |             || || || ||                  |
>         +==========================================+
>                       || || || || More external interfaces
> 
> The MAC block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
> MAC IP introduces new DMA architecture called Hyper-DMA for virtualization
> scalability.
> 
> Driver functionality specific to new MAC (DW25GMAC) is implemented in
> new file dw25gmac.c.
> 
> Management of integrated ethernet switch on this SoC is not handled by
> the PCIe interface.
> This SoC device has PCIe ethernet MAC directly attached to an integrated
> ethernet switch using XGMII interface.
> 
> v5->v6:
>    Change summary to address comments/suggestions by Serge Semin.
>    Patch1:
>      Removed the comlexity of hdma mapping in previous patch series and
>      use static DMA mapping.
>      Renamed plat_stmmacenet_data::snps_dev_id as dev_id and moved to
>      the beginning of the struct.
>    Patch2:
>      Added dw25gmac_get_hw_feature() for dw25gmac.
>      Use static one-to-one VDMA-TC-PDMA mapping.
>    Patch4:
>      Remove usage of plat_stmmacenet_data::msi_*_vec variables for
>      interrupt vector initialization.
>      Change phy_interface type to XGMII.
>      Cleanup unused macros.

Sorry for abandoning the v5 discussion for too long. I've finally
finished another urgent task, so I'll be more interactive in the next
few weeks. I'll get back to reviewing this series today or early
tomorrow.

-Serge(y)

>      
> v4->v5:
>    Summary of changes in this patch series:
>    As suggested by Serge Semin, defined common setup function for dw25gmac.
>    To accommodate early adopter DW25GMAC used in BCM8958x device, provide
>    a mechanism to override snps_id and snps_dev_id used for driver entry
>    matching in hwif.c
> 
>    Patch1:
>      Added plat_stmmacenet_data::snps_id,snps_dev_id fields - Serge Semin
>    Patch2:
>      Define common setup function for dw25gmac_setup() - Serge Semin
>      Support DW25GMAC IPs with varying VDMA/PDMA count - Abhishek Chauhan
>      Allocate and initialize hdma mapping configuration data dynamically
>      based on device's VDMA/PDMA feature capabilities in dw25gmac_setup().
>      Spelling errors in commit log, lower case 0x for hex -Amit Singh Tomar
>    Patch3:
>      Glue support in hwif.c for DW25GMAC in hwif.c - Serge Semin
>      Provide an option to override snps_id and snps_dev_id when the device
>      reports version info not conformant with driver's expectations as is
>      the case with BCM8958x device. - Serge Semin
>    Patch4:
>      Remove setup function in the glue driver - Serge Semin
>      Remove unnecessary calls pci_enable_device() and pci_set_master()
>      in dwxgmac_brcm_pci_resume() - Jakub Kicinski
>      Merge variable definitions to single line - Amit Singh Tomar
>     https://lore.kernel.org/netdev/20240904054815.1341712-1-jitendra.vegiraju@broadcom.com/
>    
> v3->v4:
>    Based on Serge's questions, received a confirmation from Synopsys that
>    the MAC IP is indeed the new 25GMAC design.
>    Renamed all references of XGMAC4 to 25GMAC.
>    The patch series is rearranged slightly as follows.
>    Patch1 (new): Define HDMA mapping data structure in kernel's stmmac.h
>    Patch2 (v3 Patch1): Adds dma_ops for dw25gmac in stmmac core
>        Renamed new files dwxgmac4.* to dw25gmac.* - Serge Semin
>        Defined new Synopsis version and device id macros for DW25GMAC.
>        Converted bit operations to FIELD_PREP macros - Russell King
>        Moved hwif.h to this patch, Sparse flagged warning - Simon Horman
>        Defined macros for hardcoded values TDPS etc - Serge Semin
>        Read number of PDMAs/VDMAs from hardware - Serge Semin
>    Patch3 (v3 Patch2): Hooks in hardware interface handling for dw25gmac
>        Resolved user_version quirks questions - Serge, Russell, Andrew
>        Added new stmmac_hw entry for DW25GMAC. - Serge
>        Added logic to override synopsis_dev_id by glue driver.
>    Patch4 (v3 Patch3): Adds PCI driver for BCM8958x device
>        Define bitmmap macros for hardcoded values - Andrew Lunn
>        Added per device software node - Andrew Lunn
>    Patch5(new/split): Adds BCM8958x driver to build system
>    https://lore.kernel.org/netdev/20240814221818.2612484-1-jitendra.vegiraju@broadcom.com/
> 
> v2->v3:
>    Addressed v2 comments from Andrew, Jakub, Russel and Simon.
>    Based on suggestion by Russel and Andrew, added software node to create
>    phylink in fixed-link mode.
>    Moved dwxgmac4 specific functions to new files dwxgmac4.c and dwxgmac4.h
>    in stmmac core module.
>    Reorganized the code to use the existing glue logic support for xgmac in
>    hwif.c and override ops functions for dwxgmac4 specific functions.
>    The patch is split into three parts.
>      Patch#1 Adds dma_ops for dwxgmac4 in stmmac core
>      Patch#2 Hooks in the hardware interface handling for dwxgmac4
>      Patch#3 Adds PCI driver for BCM8958x device
>    https://lore.kernel.org/netdev/20240802031822.1862030-1-jitendra.vegiraju@broadcom.com/
> 
> v1->v2:
>    Minor fixes to address coding style issues.
>    Sent v2 too soon by mistake, without waiting for review comments.
>    Received feedback on this version.
>    https://lore.kernel.org/netdev/20240511015924.41457-1-jitendra.vegiraju@broadcom.com/
> 
> v1:  
>    https://lore.kernel.org/netdev/20240510000331.154486-1-jitendra.vegiraju@broadcom.com/
> 
> Jitendra Vegiraju (5):
>   Add snps_id, dev_id to struct plat_stmmacenet_data
>   Add basic dw25gmac support in stmmac core
>   Integrate dw25gmac into stmmac hwif handling
>   Add PCI driver support for BCM8958x
>   Add BCM8958x driver to build system
> 
>  MAINTAINERS                                   |   8 +
>  drivers/net/ethernet/stmicro/stmmac/Kconfig   |  11 +
>  drivers/net/ethernet/stmicro/stmmac/Makefile  |   3 +-
>  drivers/net/ethernet/stmicro/stmmac/common.h  |   4 +
>  .../net/ethernet/stmicro/stmmac/dw25gmac.c    | 161 ++++++
>  .../net/ethernet/stmicro/stmmac/dw25gmac.h    |  92 ++++
>  .../net/ethernet/stmicro/stmmac/dwmac-brcm.c  | 478 ++++++++++++++++++
>  .../net/ethernet/stmicro/stmmac/dwxgmac2.h    |   1 +
>  .../ethernet/stmicro/stmmac/dwxgmac2_core.c   |  42 ++
>  .../ethernet/stmicro/stmmac/dwxgmac2_dma.c    |  52 ++
>  drivers/net/ethernet/stmicro/stmmac/hwif.c    |  26 +-
>  drivers/net/ethernet/stmicro/stmmac/hwif.h    |   1 +
>  .../net/ethernet/stmicro/stmmac/stmmac_main.c |  26 +
>  include/linux/stmmac.h                        |   2 +
>  14 files changed, 905 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
> 
> -- 
> 2.34.1
> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2024-10-21 11:05 ` [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x Serge Semin
@ 2024-10-21 16:01   ` Jitendra Vegiraju
  0 siblings, 0 replies; 19+ messages in thread
From: Jitendra Vegiraju @ 2024-10-21 16:01 UTC (permalink / raw)
  To: Serge Semin
  Cc: netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, rmk+kernel, ahalaney, xiaolei.wang,
	rohan.g.thomas, Jianheng.Zhang, linux-kernel, linux-stm32,
	linux-arm-kernel, bpf, andrew, linux, horms, florian.fainelli,
	quic_abchauha

[-- Attachment #1: Type: text/plain, Size: 847 bytes --]

Hi Serge,

On Mon, Oct 21, 2024 at 4:05 AM Serge Semin <fancer.lancer@gmail.com> wrote:
>
> Hi Jitendra
>
> On Fri, Oct 18, 2024 at 01:53:27PM GMT, jitendra.vegiraju@broadcom.com wrote:
> > From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
> >
> > This patchset adds basic PCI ethernet device driver support for Broadcom
> > BCM8958x Automotive Ethernet switch SoC devices.
> >
>
> Sorry for abandoning the v5 discussion for too long. I've finally
> finished another urgent task, so I'll be more interactive in the next
> few weeks. I'll get back to reviewing this series today or early
> tomorrow.
>
No worries. I understand, you will have to deal with multiple tasks at one time.
Sorry, if I sent the patch too soon.
Thank you for your support with our first attempt at upstreaming the work.

> -Serge(y)
>
> >

[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 5448 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core
  2024-10-18 20:53 ` [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core jitendra.vegiraju
@ 2024-10-24  1:35   ` Abhishek Chauhan (ABC)
  2024-10-24  5:21     ` Abhishek Chauhan (ABC)
  0 siblings, 1 reply; 19+ messages in thread
From: Abhishek Chauhan (ABC) @ 2024-10-24  1:35 UTC (permalink / raw)
  To: jitendra.vegiraju, netdev, Sagar Cheluvegowda
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, rmk+kernel, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, andrew, linux, horms,
	florian.fainelli, kernel



On 10/18/2024 1:53 PM, jitendra.vegiraju@broadcom.com wrote:
> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
> 
> The BCM8958x uses early adopter version of DWC_xgmac version 4.00a for
> Ethernet MAC. The DW25GMAC introduced in this version adds new DMA
> architecture called Hyper-DMA (HDMA) for virtualization scalability.
> This is realized by decoupling physical DMA channels(PDMA) from potentially
> large number of virtual DMA channels (VDMA). The VDMAs are software
> abstractions that map to PDMAs for frame transmission and reception.
> 
> Define new macros DW25GMAC_CORE_4_00 and DW25GMAC_ID to identify DW25GMAC
> device.
> To support the new HDMA architecture, a new instance of stmmac_dma_ops
> dw25gmac400_dma_ops is added.
> To support the current needs, a simple one-to-one mapping of dw25gmac's
> logical VDMA (channel) to TC to PDMAs is used.
> Most of the other dma operation functions in existing dwxgamc2_dma.c file
> are reused where applicable.
> Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core.
> 
> Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
> ---
>  drivers/net/ethernet/stmicro/stmmac/Makefile  |   2 +-
>  drivers/net/ethernet/stmicro/stmmac/common.h  |   4 +
>  .../net/ethernet/stmicro/stmmac/dw25gmac.c    | 161 ++++++++++++++++++
>  .../net/ethernet/stmicro/stmmac/dw25gmac.h    |  92 ++++++++++
>  .../net/ethernet/stmicro/stmmac/dwxgmac2.h    |   1 +
>  .../ethernet/stmicro/stmmac/dwxgmac2_core.c   |  42 +++++
>  .../ethernet/stmicro/stmmac/dwxgmac2_dma.c    |  52 ++++++
>  drivers/net/ethernet/stmicro/stmmac/hwif.h    |   1 +
>  8 files changed, 354 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
> index c2f0e91f6bf8..967e8a9aa432 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
> @@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\
>  	      mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o	\
>  	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
>  	      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
> -	      stmmac_xdp.o stmmac_est.o \
> +	      stmmac_xdp.o stmmac_est.o dw25gmac.o \
>  	      $(stmmac-y)
>  
>  stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
> index 684489156dce..9a747b89ba51 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
> @@ -38,9 +38,11 @@
>  #define DWXGMAC_CORE_2_10	0x21
>  #define DWXGMAC_CORE_2_20	0x22
>  #define DWXLGMAC_CORE_2_00	0x20
> +#define DW25GMAC_CORE_4_00	0x40
>  
>  /* Device ID */
>  #define DWXGMAC_ID		0x76
> +#define DW25GMAC_ID		0x55
>  #define DWXLGMAC_ID		0x27
>  
>  #define STMMAC_CHAN0	0	/* Always supported and default for all chips */
> @@ -563,6 +565,7 @@ struct mac_link {
>  		u32 speed2500;
>  		u32 speed5000;
>  		u32 speed10000;
> +		u32 speed25000;
>  	} xgmii;
>  	struct {
>  		u32 speed25000;
> @@ -621,6 +624,7 @@ int dwmac100_setup(struct stmmac_priv *priv);
>  int dwmac1000_setup(struct stmmac_priv *priv);
>  int dwmac4_setup(struct stmmac_priv *priv);
>  int dwxgmac2_setup(struct stmmac_priv *priv);
> +int dw25gmac_setup(struct stmmac_priv *priv);
>  int dwxlgmac2_setup(struct stmmac_priv *priv);
>  
>  void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
> new file mode 100644
> index 000000000000..8d0b45a7607a
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 Broadcom Corporation
> + */
> +#include "stmmac.h"
> +#include "dwxgmac2.h"
> +#include "dw25gmac.h"
> +
> +u32 dw25gmac_decode_vdma_count(u32 regval)
> +{
> +	/* compressed encoding for vdma count */
> +	if (regval < 16) /* Direct mapping */
> +		return regval + 1;
> +	else if (regval < 20) /* 20, 24, 28, 32 */
> +		return 20 + (regval - 16) * 4;
> +	else if (regval < 24) /* 40, 48, 56, 64 */
> +		return 40 + (regval - 20) * 8;
> +	else if (regval < 28) /* 80, 96, 112, 128 */
> +		return 80 + (regval - 24) * 16;
> +	else  /* not defined */
> +		return 0;
> +}
> +
> +static int rd_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel)
> +{
> +	u32 reg_val = 0;
> +
> +	reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
> +	reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
> +	reg_val |= XXVGMAC_CMD_TYPE | XXVGMAC_OB;
> +	writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
> +	return readl(ioaddr + XXVGMAC_DMA_CH_IND_DATA);
> +}
> +
> +static void wr_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel, u32 val)
> +{
> +	u32 reg_val = 0;
> +
> +	writel(val, ioaddr + XXVGMAC_DMA_CH_IND_DATA);
> +	reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
> +	reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
> +	reg_val |= XGMAC_OB;
> +	writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
> +}
> +
> +void dw25gmac_dma_init(void __iomem *ioaddr,
> +		       struct stmmac_dma_cfg *dma_cfg)
> +{

Adding Sagar too. 

This function expects 3 arguments and internally when we(Sagar from Qualcomm) were reviewing this patch we 
ran into compilation errors. 

Please check this function further. 


> +	u32 tx_pdmas, rx_pdmas;
> +	u32 hw_cap;
> +	u32 value;
> +	u32 i;
> +
> +	value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
> +	value &= ~(XGMAC_AAL | XGMAC_EAME);
> +	if (dma_cfg->aal)
> +		value |= XGMAC_AAL;
> +	if (dma_cfg->eame)
> +		value |= XGMAC_EAME;
> +	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
> +
> +	/* Get PDMA counts from HW */
> +	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
> +	tx_pdmas = FIELD_GET(XGMAC_HWFEAT_TXQCNT, hw_cap) + 1;
> +	rx_pdmas = FIELD_GET(XGMAC_HWFEAT_RXQCNT, hw_cap) + 1;
> +
> +	/* Intialize all PDMAs with burst length fields */
> +	for (i = 0; i < tx_pdmas; i++) {
> +		value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i);
> +		value &= ~(XXVGMAC_TXPBL | XXVGMAC_TPBLX8_MODE);
> +		if (dma_cfg->pblx8)
> +			value |= XXVGMAC_TPBLX8_MODE;
> +		value |= FIELD_PREP(XXVGMAC_TXPBL, dma_cfg->pbl);
> +		wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i, value);
> +	}
> +
> +	for (i = 0; i < rx_pdmas; i++) {
> +		value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i);
> +		value &= ~(XXVGMAC_RXPBL | XXVGMAC_RPBLX8_MODE);
> +		if (dma_cfg->pblx8)
> +			value |= XXVGMAC_RPBLX8_MODE;
> +		value |= FIELD_PREP(XXVGMAC_RXPBL, dma_cfg->pbl);
> +		wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i, value);
> +	}
> +}
> +
> +void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
> +			       void __iomem *ioaddr,
> +			       struct stmmac_dma_cfg *dma_cfg,
> +			       dma_addr_t dma_addr, u32 chan)
> +{
> +	u32 value;
> +	u32 tc;
> +
> +	/* Descriptor cache size and prefetch threshold size */
> +	value = rd_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan);
> +	value &= ~XXVGMAC_TXDCSZ;
> +	value |= FIELD_PREP(XXVGMAC_TXDCSZ,
> +			    XXVGMAC_TXDCSZ_256BYTES);
> +	value &= ~XXVGMAC_TDPS;
> +	value |= FIELD_PREP(XXVGMAC_TDPS, XXVGMAC_TDPS_HALF);
> +	wr_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan, value);
> +
> +	/* Use one-to-one mapping between VDMA, TC, and PDMA. */
> +	tc = chan;
> +
> +	/* 1-to-1 PDMA to TC mapping */
> +	value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan);
> +	value &= ~XXVGMAC_TP2TCMP;
> +	value |= FIELD_PREP(XXVGMAC_TP2TCMP, tc);
> +	wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan, value);
> +
> +	/* 1-to-1 VDMA to TC mapping */
> +	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
> +	value &= ~XXVGMAC_TVDMA2TCMP;
> +	value |= FIELD_PREP(XXVGMAC_TVDMA2TCMP, tc);
> +	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
> +
> +	writel(upper_32_bits(dma_addr),
> +	       ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
> +	writel(lower_32_bits(dma_addr),
> +	       ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
> +}
> +
> +void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
> +			       void __iomem *ioaddr,
> +			       struct stmmac_dma_cfg *dma_cfg,
> +			       dma_addr_t dma_addr, u32 chan)
> +{
> +	u32 value;
> +	u32 tc;
> +
> +	/* Descriptor cache size and prefetch threshold size */
> +	value = rd_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan);
> +	value &= ~XXVGMAC_RXDCSZ;
> +	value |= FIELD_PREP(XXVGMAC_RXDCSZ,
> +			    XXVGMAC_RXDCSZ_256BYTES);
> +	value &= ~XXVGMAC_RDPS;
> +	value |= FIELD_PREP(XXVGMAC_RDPS, XXVGMAC_RDPS_HALF);
> +	wr_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan, value);
> +
> +	/* Use one-to-one mapping between VDMA, TC, and PDMA. */
> +	tc = chan;
> +
> +	/* 1-to-1 PDMA to TC mapping */
> +	value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan);
> +	value &= ~XXVGMAC_RP2TCMP;
> +	value |= FIELD_PREP(XXVGMAC_RP2TCMP, tc);
> +	wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan, value);
> +
> +	/* 1-to-1 VDMA to TC mapping */
> +	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
> +	value &= ~XXVGMAC_RVDMA2TCMP;
> +	value |= FIELD_PREP(XXVGMAC_RVDMA2TCMP, tc);
> +	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
> +
> +	writel(upper_32_bits(dma_addr),
> +	       ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
> +	writel(lower_32_bits(dma_addr),
> +	       ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
> +}
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
> new file mode 100644
> index 000000000000..44f9601331d5
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
> @@ -0,0 +1,92 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* Copyright (c) 2024 Broadcom Corporation
> + * DW25GMAC definitions.
> + */
> +#ifndef __STMMAC_DW25GMAC_H__
> +#define __STMMAC_DW25GMAC_H__
> +
> +/* Hardware features */
> +#define XXVGMAC_HWFEAT_VDMA_RXCNT	GENMASK(16, 12)
> +#define XXVGMAC_HWFEAT_VDMA_TXCNT	GENMASK(22, 18)
> +
> +/* DMA Indirect Registers*/
> +#define XXVGMAC_DMA_CH_IND_CONTROL	0x00003080
> +#define XXVGMAC_MODE_SELECT		GENMASK(27, 24)
> +enum dma_ch_ind_modes {
> +	MODE_TXEXTCFG	 = 0x0,	  /* Tx Extended Config */
> +	MODE_RXEXTCFG	 = 0x1,	  /* Rx Extended Config */
> +	MODE_TXDBGSTS	 = 0x2,	  /* Tx Debug Status */
> +	MODE_RXDBGSTS	 = 0x3,	  /* Rx Debug Status */
> +	MODE_TXDESCCTRL	 = 0x4,	  /* Tx Descriptor control */
> +	MODE_RXDESCCTRL	 = 0x5,	  /* Rx Descriptor control */
> +};
> +
> +#define XXVGMAC_ADDR_OFFSET		GENMASK(14, 8)
> +#define XXVGMAC_AUTO_INCR		GENMASK(5, 4)
> +#define XXVGMAC_CMD_TYPE		BIT(1)
> +#define XXVGMAC_OB			BIT(0)
> +#define XXVGMAC_DMA_CH_IND_DATA		0x00003084
> +
> +/* TX Config definitions */
> +#define XXVGMAC_TXPBL			GENMASK(29, 24)
> +#define XXVGMAC_TPBLX8_MODE		BIT(19)
> +#define XXVGMAC_TP2TCMP			GENMASK(18, 16)
> +#define XXVGMAC_ORRQ			GENMASK(13, 8)
> +
> +/* RX Config definitions */
> +#define XXVGMAC_RXPBL			GENMASK(29, 24)
> +#define XXVGMAC_RPBLX8_MODE		BIT(19)
> +#define XXVGMAC_RP2TCMP			GENMASK(18, 16)
> +#define XXVGMAC_OWRQ			GENMASK(13, 8)
> +
> +/* Tx Descriptor control */
> +#define XXVGMAC_TXDCSZ			GENMASK(2, 0)
> +#define XXVGMAC_TXDCSZ_0BYTES		0
> +#define XXVGMAC_TXDCSZ_64BYTES		1
> +#define XXVGMAC_TXDCSZ_128BYTES		2
> +#define XXVGMAC_TXDCSZ_256BYTES		3
> +#define XXVGMAC_TDPS			GENMASK(5, 3)
> +#define XXVGMAC_TDPS_ZERO		0
> +#define XXVGMAC_TDPS_1_8TH		1
> +#define XXVGMAC_TDPS_1_4TH		2
> +#define XXVGMAC_TDPS_HALF		3
> +#define XXVGMAC_TDPS_3_4TH		4
> +
> +/* Rx Descriptor control */
> +#define XXVGMAC_RXDCSZ			GENMASK(2, 0)
> +#define XXVGMAC_RXDCSZ_0BYTES		0
> +#define XXVGMAC_RXDCSZ_64BYTES		1
> +#define XXVGMAC_RXDCSZ_128BYTES		2
> +#define XXVGMAC_RXDCSZ_256BYTES		3
> +#define XXVGMAC_RDPS			GENMASK(5, 3)
> +#define XXVGMAC_RDPS_ZERO		0
> +#define XXVGMAC_RDPS_1_8TH		1
> +#define XXVGMAC_RDPS_1_4TH		2
> +#define XXVGMAC_RDPS_HALF		3
> +#define XXVGMAC_RDPS_3_4TH		4
> +
> +/* DWCXG_DMA_CH(#i) Registers*/
> +#define XXVGMAC_DSL			GENMASK(20, 18)
> +#define XXVGMAC_MSS			GENMASK(13, 0)
> +#define XXVGMAC_TFSEL			GENMASK(30, 29)
> +#define XXVGMAC_TQOS			GENMASK(27, 24)
> +#define XXVGMAC_IPBL			BIT(15)
> +#define XXVGMAC_TVDMA2TCMP		GENMASK(6, 4)
> +#define XXVGMAC_RPF			BIT(31)
> +#define XXVGMAC_RVDMA2TCMP		GENMASK(30, 28)
> +#define XXVGMAC_RQOS			GENMASK(27, 24)
> +
> +u32 dw25gmac_decode_vdma_count(u32 regval);
> +
> +void dw25gmac_dma_init(void __iomem *ioaddr,
> +		       struct stmmac_dma_cfg *dma_cfg);
> +
> +void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
> +			       void __iomem *ioaddr,
> +			       struct stmmac_dma_cfg *dma_cfg,
> +			       dma_addr_t dma_addr, u32 chan);
> +void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
> +			       void __iomem *ioaddr,
> +			       struct stmmac_dma_cfg *dma_cfg,
> +			       dma_addr_t dma_addr, u32 chan);
> +#endif /* __STMMAC_DW25GMAC_H__ */
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
> index 6a2c7d22df1e..c9424c5a6ce5 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
> @@ -17,6 +17,7 @@
>  #define XGMAC_CONFIG_SS_OFF		29
>  #define XGMAC_CONFIG_SS_MASK		GENMASK(31, 29)
>  #define XGMAC_CONFIG_SS_10000		(0x0 << XGMAC_CONFIG_SS_OFF)
> +#define XGMAC_CONFIG_SS_25000		(0x1 << XGMAC_CONFIG_SS_OFF)
>  #define XGMAC_CONFIG_SS_2500_GMII	(0x2 << XGMAC_CONFIG_SS_OFF)
>  #define XGMAC_CONFIG_SS_1000_GMII	(0x3 << XGMAC_CONFIG_SS_OFF)
>  #define XGMAC_CONFIG_SS_100_MII		(0x4 << XGMAC_CONFIG_SS_OFF)
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> index f519d43738b0..96013b489af6 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> @@ -11,6 +11,7 @@
>  #include "stmmac_ptp.h"
>  #include "dwxlgmac2.h"
>  #include "dwxgmac2.h"
> +#include "dw25gmac.h"
>  
>  static void dwxgmac2_core_init(struct mac_device_info *hw,
>  			       struct net_device *dev)
> @@ -1670,6 +1671,47 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
>  	return 0;
>  }
>  
> +int dw25gmac_setup(struct stmmac_priv *priv)
> +{
> +	struct mac_device_info *mac = priv->hw;
> +
> +	dev_info(priv->device, "\tDW25GMAC\n");
> +
> +	priv->dev->priv_flags |= IFF_UNICAST_FLT;
> +	mac->pcsr = priv->ioaddr;
> +	mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
> +	mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
> +	mac->mcast_bits_log2 = 0;
> +
> +	if (mac->multicast_filter_bins)
> +		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
> +
> +	mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> +			 MAC_1000FD | MAC_2500FD | MAC_5000FD |
> +			 MAC_10000FD | MAC_25000FD;
> +	mac->link.duplex = 0;
> +	mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
> +	mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
> +	mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
> +	mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
> +	mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
> +	mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
> +	mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
> +	mac->link.xgmii.speed25000 = XGMAC_CONFIG_SS_25000;
> +	mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
> +
> +	mac->mii.addr = XGMAC_MDIO_ADDR;
> +	mac->mii.data = XGMAC_MDIO_DATA;
> +	mac->mii.addr_shift = 16;
> +	mac->mii.addr_mask = GENMASK(20, 16);
> +	mac->mii.reg_shift = 0;
> +	mac->mii.reg_mask = GENMASK(15, 0);
> +	mac->mii.clk_csr_shift = 19;
> +	mac->mii.clk_csr_mask = GENMASK(21, 19);
> +
> +	return 0;
> +}
> +
>  int dwxlgmac2_setup(struct stmmac_priv *priv)
>  {
>  	struct mac_device_info *mac = priv->hw;
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> index 7840bc403788..2e86eaafd16e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> @@ -7,6 +7,7 @@
>  #include <linux/iopoll.h>
>  #include "stmmac.h"
>  #include "dwxgmac2.h"
> +#include "dw25gmac.h"
>  
>  static int dwxgmac2_dma_reset(void __iomem *ioaddr)
>  {
> @@ -500,6 +501,27 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
>  	return 0;
>  }
>  
> +static int dw25gmac_get_hw_feature(void __iomem *ioaddr,
> +				   struct dma_features *dma_cap)
> +
> +{
> +	u32 hw_cap;
> +	int ret;
> +
> +	ret = dwxgmac2_get_hw_feature(ioaddr, dma_cap);
> +
> +	/* For DW25GMAC VDMA channel count is channel count */
> +	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
> +	dma_cap->number_tx_channel =
> +		dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_TXCNT,
> +					    hw_cap));
> +	dma_cap->number_rx_channel =
> +		dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_RXCNT,
> +					    hw_cap));
> +
> +	return ret;
> +}
> +
>  static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
>  				 u32 riwt, u32 queue)
>  {
> @@ -641,3 +663,33 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = {
>  	.enable_sph = dwxgmac2_enable_sph,
>  	.enable_tbs = dwxgmac2_enable_tbs,
>  };
> +
> +const struct stmmac_dma_ops dw25gmac400_dma_ops = {
> +	.reset = dwxgmac2_dma_reset,
> +	.init = dw25gmac_dma_init,
> +	.init_chan = dwxgmac2_dma_init_chan,
> +	.init_rx_chan = dw25gmac_dma_init_rx_chan,
> +	.init_tx_chan = dw25gmac_dma_init_tx_chan,
> +	.axi = dwxgmac2_dma_axi,
> +	.dump_regs = dwxgmac2_dma_dump_regs,
> +	.dma_rx_mode = dwxgmac2_dma_rx_mode,
> +	.dma_tx_mode = dwxgmac2_dma_tx_mode,
> +	.enable_dma_irq = dwxgmac2_enable_dma_irq,
> +	.disable_dma_irq = dwxgmac2_disable_dma_irq,
> +	.start_tx = dwxgmac2_dma_start_tx,
> +	.stop_tx = dwxgmac2_dma_stop_tx,
> +	.start_rx = dwxgmac2_dma_start_rx,
> +	.stop_rx = dwxgmac2_dma_stop_rx,
> +	.dma_interrupt = dwxgmac2_dma_interrupt,
> +	.get_hw_feature = dw25gmac_get_hw_feature,
> +	.rx_watchdog = dwxgmac2_rx_watchdog,
> +	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
> +	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
> +	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
> +	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
> +	.enable_tso = dwxgmac2_enable_tso,
> +	.qmode = dwxgmac2_qmode,
> +	.set_bfsize = dwxgmac2_set_bfsize,
> +	.enable_sph = dwxgmac2_enable_sph,
> +	.enable_tbs = dwxgmac2_enable_tbs,
> +};
> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
> index d5a9f01ecac5..774ea8cd5ae9 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
> @@ -702,6 +702,7 @@ extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
>  extern const struct stmmac_mmc_ops dwmac_mmc_ops;
>  extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;
>  extern const struct stmmac_est_ops dwmac510_est_ops;
> +extern const struct stmmac_dma_ops dw25gmac400_dma_ops;
>  
>  #define GMAC_VERSION		0x00000020	/* GMAC CORE Version */
>  #define GMAC4_VERSION		0x00000110	/* GMAC4+ CORE Version */

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core
  2024-10-24  1:35   ` Abhishek Chauhan (ABC)
@ 2024-10-24  5:21     ` Abhishek Chauhan (ABC)
  0 siblings, 0 replies; 19+ messages in thread
From: Abhishek Chauhan (ABC) @ 2024-10-24  5:21 UTC (permalink / raw)
  To: jitendra.vegiraju, netdev, Sagar Cheluvegowda
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, rmk+kernel,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, andrew, linux, horms,
	florian.fainelli, kernel



On 10/23/2024 6:35 PM, Abhishek Chauhan (ABC) wrote:
> 
> 
> On 10/18/2024 1:53 PM, jitendra.vegiraju@broadcom.com wrote:
>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>>
>> The BCM8958x uses early adopter version of DWC_xgmac version 4.00a for
>> Ethernet MAC. The DW25GMAC introduced in this version adds new DMA
>> architecture called Hyper-DMA (HDMA) for virtualization scalability.
>> This is realized by decoupling physical DMA channels(PDMA) from potentially
>> large number of virtual DMA channels (VDMA). The VDMAs are software
>> abstractions that map to PDMAs for frame transmission and reception.
>>
>> Define new macros DW25GMAC_CORE_4_00 and DW25GMAC_ID to identify DW25GMAC
>> device.
>> To support the new HDMA architecture, a new instance of stmmac_dma_ops
>> dw25gmac400_dma_ops is added.
>> To support the current needs, a simple one-to-one mapping of dw25gmac's
>> logical VDMA (channel) to TC to PDMAs is used.
>> Most of the other dma operation functions in existing dwxgamc2_dma.c file
>> are reused where applicable.
>> Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core.
>>
>> Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>> ---
>>  drivers/net/ethernet/stmicro/stmmac/Makefile  |   2 +-
>>  drivers/net/ethernet/stmicro/stmmac/common.h  |   4 +
>>  .../net/ethernet/stmicro/stmmac/dw25gmac.c    | 161 ++++++++++++++++++
>>  .../net/ethernet/stmicro/stmmac/dw25gmac.h    |  92 ++++++++++
>>  .../net/ethernet/stmicro/stmmac/dwxgmac2.h    |   1 +
>>  .../ethernet/stmicro/stmmac/dwxgmac2_core.c   |  42 +++++
>>  .../ethernet/stmicro/stmmac/dwxgmac2_dma.c    |  52 ++++++
>>  drivers/net/ethernet/stmicro/stmmac/hwif.h    |   1 +
>>  8 files changed, 354 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
>>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
>> index c2f0e91f6bf8..967e8a9aa432 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
>> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
>> @@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\
>>  	      mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o	\
>>  	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
>>  	      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
>> -	      stmmac_xdp.o stmmac_est.o \
>> +	      stmmac_xdp.o stmmac_est.o dw25gmac.o \
>>  	      $(stmmac-y)
>>  
>>  stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
>> index 684489156dce..9a747b89ba51 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
>> @@ -38,9 +38,11 @@
>>  #define DWXGMAC_CORE_2_10	0x21
>>  #define DWXGMAC_CORE_2_20	0x22
>>  #define DWXLGMAC_CORE_2_00	0x20
>> +#define DW25GMAC_CORE_4_00	0x40
>>  
>>  /* Device ID */
>>  #define DWXGMAC_ID		0x76
>> +#define DW25GMAC_ID		0x55
>>  #define DWXLGMAC_ID		0x27
>>  
>>  #define STMMAC_CHAN0	0	/* Always supported and default for all chips */
>> @@ -563,6 +565,7 @@ struct mac_link {
>>  		u32 speed2500;
>>  		u32 speed5000;
>>  		u32 speed10000;
>> +		u32 speed25000;
>>  	} xgmii;
>>  	struct {
>>  		u32 speed25000;
>> @@ -621,6 +624,7 @@ int dwmac100_setup(struct stmmac_priv *priv);
>>  int dwmac1000_setup(struct stmmac_priv *priv);
>>  int dwmac4_setup(struct stmmac_priv *priv);
>>  int dwxgmac2_setup(struct stmmac_priv *priv);
>> +int dw25gmac_setup(struct stmmac_priv *priv);
>>  int dwxlgmac2_setup(struct stmmac_priv *priv);
>>  
>>  void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
>> new file mode 100644
>> index 000000000000..8d0b45a7607a
>> --- /dev/null
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
>> @@ -0,0 +1,161 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2024 Broadcom Corporation
>> + */
>> +#include "stmmac.h"
>> +#include "dwxgmac2.h"
>> +#include "dw25gmac.h"
>> +
>> +u32 dw25gmac_decode_vdma_count(u32 regval)
>> +{
>> +	/* compressed encoding for vdma count */
>> +	if (regval < 16) /* Direct mapping */
>> +		return regval + 1;
>> +	else if (regval < 20) /* 20, 24, 28, 32 */
>> +		return 20 + (regval - 16) * 4;
>> +	else if (regval < 24) /* 40, 48, 56, 64 */
>> +		return 40 + (regval - 20) * 8;
>> +	else if (regval < 28) /* 80, 96, 112, 128 */
>> +		return 80 + (regval - 24) * 16;
>> +	else  /* not defined */
>> +		return 0;
>> +}
>> +
>> +static int rd_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel)
>> +{
>> +	u32 reg_val = 0;
>> +
>> +	reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
>> +	reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
>> +	reg_val |= XXVGMAC_CMD_TYPE | XXVGMAC_OB;
>> +	writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
>> +	return readl(ioaddr + XXVGMAC_DMA_CH_IND_DATA);
>> +}
>> +
>> +static void wr_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel, u32 val)
>> +{
>> +	u32 reg_val = 0;
>> +
>> +	writel(val, ioaddr + XXVGMAC_DMA_CH_IND_DATA);
>> +	reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
>> +	reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
>> +	reg_val |= XGMAC_OB;
>> +	writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
>> +}
>> +
>> +void dw25gmac_dma_init(void __iomem *ioaddr,
>> +		       struct stmmac_dma_cfg *dma_cfg)
>> +{
> 
> Adding Sagar too. 
> 
> This function expects 3 arguments and internally when we(Sagar from Qualcomm) were reviewing this patch we 
> ran into compilation errors. 
> 
> Please check this function further. 
> 

Sorry my bad. You are good. Latest kernel has only two arguments. Sorry for the confusion. 

> 
>> +	u32 tx_pdmas, rx_pdmas;
>> +	u32 hw_cap;
>> +	u32 value;
>> +	u32 i;
>> +
>> +	value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
>> +	value &= ~(XGMAC_AAL | XGMAC_EAME);
>> +	if (dma_cfg->aal)
>> +		value |= XGMAC_AAL;
>> +	if (dma_cfg->eame)
>> +		value |= XGMAC_EAME;
>> +	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
>> +
>> +	/* Get PDMA counts from HW */
>> +	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
>> +	tx_pdmas = FIELD_GET(XGMAC_HWFEAT_TXQCNT, hw_cap) + 1;
>> +	rx_pdmas = FIELD_GET(XGMAC_HWFEAT_RXQCNT, hw_cap) + 1;
>> +
>> +	/* Intialize all PDMAs with burst length fields */
>> +	for (i = 0; i < tx_pdmas; i++) {
>> +		value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i);
>> +		value &= ~(XXVGMAC_TXPBL | XXVGMAC_TPBLX8_MODE);
>> +		if (dma_cfg->pblx8)
>> +			value |= XXVGMAC_TPBLX8_MODE;
>> +		value |= FIELD_PREP(XXVGMAC_TXPBL, dma_cfg->pbl);
>> +		wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i, value);
>> +	}
>> +
>> +	for (i = 0; i < rx_pdmas; i++) {
>> +		value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i);
>> +		value &= ~(XXVGMAC_RXPBL | XXVGMAC_RPBLX8_MODE);
>> +		if (dma_cfg->pblx8)
>> +			value |= XXVGMAC_RPBLX8_MODE;
>> +		value |= FIELD_PREP(XXVGMAC_RXPBL, dma_cfg->pbl);
>> +		wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i, value);
>> +	}
>> +}
>> +
>> +void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
>> +			       void __iomem *ioaddr,
>> +			       struct stmmac_dma_cfg *dma_cfg,
>> +			       dma_addr_t dma_addr, u32 chan)
>> +{
>> +	u32 value;
>> +	u32 tc;
>> +
>> +	/* Descriptor cache size and prefetch threshold size */
>> +	value = rd_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan);
>> +	value &= ~XXVGMAC_TXDCSZ;
>> +	value |= FIELD_PREP(XXVGMAC_TXDCSZ,
>> +			    XXVGMAC_TXDCSZ_256BYTES);
>> +	value &= ~XXVGMAC_TDPS;
>> +	value |= FIELD_PREP(XXVGMAC_TDPS, XXVGMAC_TDPS_HALF);
>> +	wr_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan, value);
>> +
>> +	/* Use one-to-one mapping between VDMA, TC, and PDMA. */
>> +	tc = chan;
>> +
>> +	/* 1-to-1 PDMA to TC mapping */
>> +	value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan);
>> +	value &= ~XXVGMAC_TP2TCMP;
>> +	value |= FIELD_PREP(XXVGMAC_TP2TCMP, tc);
>> +	wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan, value);
>> +
>> +	/* 1-to-1 VDMA to TC mapping */
>> +	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
>> +	value &= ~XXVGMAC_TVDMA2TCMP;
>> +	value |= FIELD_PREP(XXVGMAC_TVDMA2TCMP, tc);
>> +	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
>> +
>> +	writel(upper_32_bits(dma_addr),
>> +	       ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
>> +	writel(lower_32_bits(dma_addr),
>> +	       ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
>> +}
>> +
>> +void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
>> +			       void __iomem *ioaddr,
>> +			       struct stmmac_dma_cfg *dma_cfg,
>> +			       dma_addr_t dma_addr, u32 chan)
>> +{
>> +	u32 value;
>> +	u32 tc;
>> +
>> +	/* Descriptor cache size and prefetch threshold size */
>> +	value = rd_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan);
>> +	value &= ~XXVGMAC_RXDCSZ;
>> +	value |= FIELD_PREP(XXVGMAC_RXDCSZ,
>> +			    XXVGMAC_RXDCSZ_256BYTES);
>> +	value &= ~XXVGMAC_RDPS;
>> +	value |= FIELD_PREP(XXVGMAC_RDPS, XXVGMAC_RDPS_HALF);
>> +	wr_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan, value);
>> +
>> +	/* Use one-to-one mapping between VDMA, TC, and PDMA. */
>> +	tc = chan;
>> +
>> +	/* 1-to-1 PDMA to TC mapping */
>> +	value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan);
>> +	value &= ~XXVGMAC_RP2TCMP;
>> +	value |= FIELD_PREP(XXVGMAC_RP2TCMP, tc);
>> +	wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan, value);
>> +
>> +	/* 1-to-1 VDMA to TC mapping */
>> +	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
>> +	value &= ~XXVGMAC_RVDMA2TCMP;
>> +	value |= FIELD_PREP(XXVGMAC_RVDMA2TCMP, tc);
>> +	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
>> +
>> +	writel(upper_32_bits(dma_addr),
>> +	       ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
>> +	writel(lower_32_bits(dma_addr),
>> +	       ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
>> +}
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
>> new file mode 100644
>> index 000000000000..44f9601331d5
>> --- /dev/null
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
>> @@ -0,0 +1,92 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/* Copyright (c) 2024 Broadcom Corporation
>> + * DW25GMAC definitions.
>> + */
>> +#ifndef __STMMAC_DW25GMAC_H__
>> +#define __STMMAC_DW25GMAC_H__
>> +
>> +/* Hardware features */
>> +#define XXVGMAC_HWFEAT_VDMA_RXCNT	GENMASK(16, 12)
>> +#define XXVGMAC_HWFEAT_VDMA_TXCNT	GENMASK(22, 18)
>> +
>> +/* DMA Indirect Registers*/
>> +#define XXVGMAC_DMA_CH_IND_CONTROL	0x00003080
>> +#define XXVGMAC_MODE_SELECT		GENMASK(27, 24)
>> +enum dma_ch_ind_modes {
>> +	MODE_TXEXTCFG	 = 0x0,	  /* Tx Extended Config */
>> +	MODE_RXEXTCFG	 = 0x1,	  /* Rx Extended Config */
>> +	MODE_TXDBGSTS	 = 0x2,	  /* Tx Debug Status */
>> +	MODE_RXDBGSTS	 = 0x3,	  /* Rx Debug Status */
>> +	MODE_TXDESCCTRL	 = 0x4,	  /* Tx Descriptor control */
>> +	MODE_RXDESCCTRL	 = 0x5,	  /* Rx Descriptor control */
>> +};
>> +
>> +#define XXVGMAC_ADDR_OFFSET		GENMASK(14, 8)
>> +#define XXVGMAC_AUTO_INCR		GENMASK(5, 4)
>> +#define XXVGMAC_CMD_TYPE		BIT(1)
>> +#define XXVGMAC_OB			BIT(0)
>> +#define XXVGMAC_DMA_CH_IND_DATA		0x00003084
>> +
>> +/* TX Config definitions */
>> +#define XXVGMAC_TXPBL			GENMASK(29, 24)
>> +#define XXVGMAC_TPBLX8_MODE		BIT(19)
>> +#define XXVGMAC_TP2TCMP			GENMASK(18, 16)
>> +#define XXVGMAC_ORRQ			GENMASK(13, 8)
>> +
>> +/* RX Config definitions */
>> +#define XXVGMAC_RXPBL			GENMASK(29, 24)
>> +#define XXVGMAC_RPBLX8_MODE		BIT(19)
>> +#define XXVGMAC_RP2TCMP			GENMASK(18, 16)
>> +#define XXVGMAC_OWRQ			GENMASK(13, 8)
>> +
>> +/* Tx Descriptor control */
>> +#define XXVGMAC_TXDCSZ			GENMASK(2, 0)
>> +#define XXVGMAC_TXDCSZ_0BYTES		0
>> +#define XXVGMAC_TXDCSZ_64BYTES		1
>> +#define XXVGMAC_TXDCSZ_128BYTES		2
>> +#define XXVGMAC_TXDCSZ_256BYTES		3
>> +#define XXVGMAC_TDPS			GENMASK(5, 3)
>> +#define XXVGMAC_TDPS_ZERO		0
>> +#define XXVGMAC_TDPS_1_8TH		1
>> +#define XXVGMAC_TDPS_1_4TH		2
>> +#define XXVGMAC_TDPS_HALF		3
>> +#define XXVGMAC_TDPS_3_4TH		4
>> +
>> +/* Rx Descriptor control */
>> +#define XXVGMAC_RXDCSZ			GENMASK(2, 0)
>> +#define XXVGMAC_RXDCSZ_0BYTES		0
>> +#define XXVGMAC_RXDCSZ_64BYTES		1
>> +#define XXVGMAC_RXDCSZ_128BYTES		2
>> +#define XXVGMAC_RXDCSZ_256BYTES		3
>> +#define XXVGMAC_RDPS			GENMASK(5, 3)
>> +#define XXVGMAC_RDPS_ZERO		0
>> +#define XXVGMAC_RDPS_1_8TH		1
>> +#define XXVGMAC_RDPS_1_4TH		2
>> +#define XXVGMAC_RDPS_HALF		3
>> +#define XXVGMAC_RDPS_3_4TH		4
>> +
>> +/* DWCXG_DMA_CH(#i) Registers*/
>> +#define XXVGMAC_DSL			GENMASK(20, 18)
>> +#define XXVGMAC_MSS			GENMASK(13, 0)
>> +#define XXVGMAC_TFSEL			GENMASK(30, 29)
>> +#define XXVGMAC_TQOS			GENMASK(27, 24)
>> +#define XXVGMAC_IPBL			BIT(15)
>> +#define XXVGMAC_TVDMA2TCMP		GENMASK(6, 4)
>> +#define XXVGMAC_RPF			BIT(31)
>> +#define XXVGMAC_RVDMA2TCMP		GENMASK(30, 28)
>> +#define XXVGMAC_RQOS			GENMASK(27, 24)
>> +
>> +u32 dw25gmac_decode_vdma_count(u32 regval);
>> +
>> +void dw25gmac_dma_init(void __iomem *ioaddr,
>> +		       struct stmmac_dma_cfg *dma_cfg);
>> +
>> +void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
>> +			       void __iomem *ioaddr,
>> +			       struct stmmac_dma_cfg *dma_cfg,
>> +			       dma_addr_t dma_addr, u32 chan);
>> +void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
>> +			       void __iomem *ioaddr,
>> +			       struct stmmac_dma_cfg *dma_cfg,
>> +			       dma_addr_t dma_addr, u32 chan);
>> +#endif /* __STMMAC_DW25GMAC_H__ */
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
>> index 6a2c7d22df1e..c9424c5a6ce5 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
>> @@ -17,6 +17,7 @@
>>  #define XGMAC_CONFIG_SS_OFF		29
>>  #define XGMAC_CONFIG_SS_MASK		GENMASK(31, 29)
>>  #define XGMAC_CONFIG_SS_10000		(0x0 << XGMAC_CONFIG_SS_OFF)
>> +#define XGMAC_CONFIG_SS_25000		(0x1 << XGMAC_CONFIG_SS_OFF)
>>  #define XGMAC_CONFIG_SS_2500_GMII	(0x2 << XGMAC_CONFIG_SS_OFF)
>>  #define XGMAC_CONFIG_SS_1000_GMII	(0x3 << XGMAC_CONFIG_SS_OFF)
>>  #define XGMAC_CONFIG_SS_100_MII		(0x4 << XGMAC_CONFIG_SS_OFF)
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
>> index f519d43738b0..96013b489af6 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
>> @@ -11,6 +11,7 @@
>>  #include "stmmac_ptp.h"
>>  #include "dwxlgmac2.h"
>>  #include "dwxgmac2.h"
>> +#include "dw25gmac.h"
>>  
>>  static void dwxgmac2_core_init(struct mac_device_info *hw,
>>  			       struct net_device *dev)
>> @@ -1670,6 +1671,47 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
>>  	return 0;
>>  }
>>  
>> +int dw25gmac_setup(struct stmmac_priv *priv)
>> +{
>> +	struct mac_device_info *mac = priv->hw;
>> +
>> +	dev_info(priv->device, "\tDW25GMAC\n");
>> +
>> +	priv->dev->priv_flags |= IFF_UNICAST_FLT;
>> +	mac->pcsr = priv->ioaddr;
>> +	mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
>> +	mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
>> +	mac->mcast_bits_log2 = 0;
>> +
>> +	if (mac->multicast_filter_bins)
>> +		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
>> +
>> +	mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
>> +			 MAC_1000FD | MAC_2500FD | MAC_5000FD |
>> +			 MAC_10000FD | MAC_25000FD;
>> +	mac->link.duplex = 0;
>> +	mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
>> +	mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
>> +	mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
>> +	mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
>> +	mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
>> +	mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
>> +	mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
>> +	mac->link.xgmii.speed25000 = XGMAC_CONFIG_SS_25000;
>> +	mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
>> +
>> +	mac->mii.addr = XGMAC_MDIO_ADDR;
>> +	mac->mii.data = XGMAC_MDIO_DATA;
>> +	mac->mii.addr_shift = 16;
>> +	mac->mii.addr_mask = GENMASK(20, 16);
>> +	mac->mii.reg_shift = 0;
>> +	mac->mii.reg_mask = GENMASK(15, 0);
>> +	mac->mii.clk_csr_shift = 19;
>> +	mac->mii.clk_csr_mask = GENMASK(21, 19);
>> +
>> +	return 0;
>> +}
>> +
>>  int dwxlgmac2_setup(struct stmmac_priv *priv)
>>  {
>>  	struct mac_device_info *mac = priv->hw;
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
>> index 7840bc403788..2e86eaafd16e 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
>> @@ -7,6 +7,7 @@
>>  #include <linux/iopoll.h>
>>  #include "stmmac.h"
>>  #include "dwxgmac2.h"
>> +#include "dw25gmac.h"
>>  
>>  static int dwxgmac2_dma_reset(void __iomem *ioaddr)
>>  {
>> @@ -500,6 +501,27 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
>>  	return 0;
>>  }
>>  
>> +static int dw25gmac_get_hw_feature(void __iomem *ioaddr,
>> +				   struct dma_features *dma_cap)
>> +
>> +{
>> +	u32 hw_cap;
>> +	int ret;
>> +
>> +	ret = dwxgmac2_get_hw_feature(ioaddr, dma_cap);
>> +
>> +	/* For DW25GMAC VDMA channel count is channel count */
>> +	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
>> +	dma_cap->number_tx_channel =
>> +		dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_TXCNT,
>> +					    hw_cap));
>> +	dma_cap->number_rx_channel =
>> +		dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_RXCNT,
>> +					    hw_cap));
>> +
>> +	return ret;
>> +}
>> +
>>  static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
>>  				 u32 riwt, u32 queue)
>>  {
>> @@ -641,3 +663,33 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = {
>>  	.enable_sph = dwxgmac2_enable_sph,
>>  	.enable_tbs = dwxgmac2_enable_tbs,
>>  };
>> +
>> +const struct stmmac_dma_ops dw25gmac400_dma_ops = {
>> +	.reset = dwxgmac2_dma_reset,
>> +	.init = dw25gmac_dma_init,
>> +	.init_chan = dwxgmac2_dma_init_chan,
>> +	.init_rx_chan = dw25gmac_dma_init_rx_chan,
>> +	.init_tx_chan = dw25gmac_dma_init_tx_chan,
>> +	.axi = dwxgmac2_dma_axi,
>> +	.dump_regs = dwxgmac2_dma_dump_regs,
>> +	.dma_rx_mode = dwxgmac2_dma_rx_mode,
>> +	.dma_tx_mode = dwxgmac2_dma_tx_mode,
>> +	.enable_dma_irq = dwxgmac2_enable_dma_irq,
>> +	.disable_dma_irq = dwxgmac2_disable_dma_irq,
>> +	.start_tx = dwxgmac2_dma_start_tx,
>> +	.stop_tx = dwxgmac2_dma_stop_tx,
>> +	.start_rx = dwxgmac2_dma_start_rx,
>> +	.stop_rx = dwxgmac2_dma_stop_rx,
>> +	.dma_interrupt = dwxgmac2_dma_interrupt,
>> +	.get_hw_feature = dw25gmac_get_hw_feature,
>> +	.rx_watchdog = dwxgmac2_rx_watchdog,
>> +	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
>> +	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
>> +	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
>> +	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
>> +	.enable_tso = dwxgmac2_enable_tso,
>> +	.qmode = dwxgmac2_qmode,
>> +	.set_bfsize = dwxgmac2_set_bfsize,
>> +	.enable_sph = dwxgmac2_enable_sph,
>> +	.enable_tbs = dwxgmac2_enable_tbs,
>> +};
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
>> index d5a9f01ecac5..774ea8cd5ae9 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
>> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
>> @@ -702,6 +702,7 @@ extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
>>  extern const struct stmmac_mmc_ops dwmac_mmc_ops;
>>  extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;
>>  extern const struct stmmac_est_ops dwmac510_est_ops;
>> +extern const struct stmmac_dma_ops dw25gmac400_dma_ops;
>>  
>>  #define GMAC_VERSION		0x00000020	/* GMAC CORE Version */
>>  #define GMAC4_VERSION		0x00000110	/* GMAC4+ CORE Version */

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
                   ` (5 preceding siblings ...)
  2024-10-21 11:05 ` [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x Serge Semin
@ 2024-11-05 16:12 ` Jitendra Vegiraju
  2025-02-07 18:21   ` Abhishek Chauhan (ABC)
  6 siblings, 1 reply; 19+ messages in thread
From: Jitendra Vegiraju @ 2024-11-05 16:12 UTC (permalink / raw)
  To: netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, rmk+kernel, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, andrew, linux, horms,
	florian.fainelli, quic_abchauha

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Hi netdev team,

On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
>
> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>
> This patchset adds basic PCI ethernet device driver support for Broadcom
> BCM8958x Automotive Ethernet switch SoC devices.
>
> This SoC device has PCIe ethernet MAC attached to an integrated ethernet
> switch using XGMII interface. The PCIe ethernet controller is presented to
> the Linux host as PCI network device.
>
> The following block diagram gives an overview of the application.
>              +=================================+
>              |       Host CPU/Linux            |
>              +=================================+
>                         || PCIe
>                         ||
>         +==========================================+
>         |           +--------------+               |
>         |           | PCIE Endpoint|               |
>         |           | Ethernet     |               |
>         |           | Controller   |               |
>         |           |   DMA        |               |
>         |           +--------------+               |
>         |           |   MAC        |   BCM8958X    |
>         |           +--------------+   SoC         |
>         |               || XGMII                   |
>         |               ||                         |
>         |           +--------------+               |
>         |           | Ethernet     |               |
>         |           | switch       |               |
>         |           +--------------+               |
>         |             || || || ||                  |
>         +==========================================+
>                       || || || || More external interfaces
>
> The MAC block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
> MAC IP introduces new DMA architecture called Hyper-DMA for virtualization
> scalability.
>
> Driver functionality specific to new MAC (DW25GMAC) is implemented in
> new file dw25gmac.c.
>
> Management of integrated ethernet switch on this SoC is not handled by
> the PCIe interface.
> This SoC device has PCIe ethernet MAC directly attached to an integrated
> ethernet switch using XGMII interface.
>
> v5->v6:
>    Change summary to address comments/suggestions by Serge Semin.
>    Patch1:
>      Removed the comlexity of hdma mapping in previous patch series and
>      use static DMA mapping.
>      Renamed plat_stmmacenet_data::snps_dev_id as dev_id and moved to
>      the beginning of the struct.
>    Patch2:
>      Added dw25gmac_get_hw_feature() for dw25gmac.
>      Use static one-to-one VDMA-TC-PDMA mapping.
>    Patch4:
>      Remove usage of plat_stmmacenet_data::msi_*_vec variables for
>      interrupt vector initialization.
>      Change phy_interface type to XGMII.
>      Cleanup unused macros.
>

I would like to seek your guidance on how to take this patch series forward.
Thanks to your feedback and Serge's suggestions, we made some forward
progress on this patch series.
Please make any suggestions to enable us to upstream driver support
for BCM8958x.
Thanks,
Jitendra

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2024-11-05 16:12 ` Jitendra Vegiraju
@ 2025-02-07 18:21   ` Abhishek Chauhan (ABC)
  2025-02-07 23:18     ` Jitendra Vegiraju
  0 siblings, 1 reply; 19+ messages in thread
From: Abhishek Chauhan (ABC) @ 2025-02-07 18:21 UTC (permalink / raw)
  To: Jitendra Vegiraju, netdev
  Cc: alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, rmk+kernel, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, andrew, linux, horms,
	florian.fainelli



On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
> Hi netdev team,
> 
> On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
>>
>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>>
>> This patchset adds basic PCI ethernet device driver support for Broadcom
>> BCM8958x Automotive Ethernet switch SoC devices.
>>
>> This SoC device has PCIe ethernet MAC attached to an integrated ethernet
>> switch using XGMII interface. The PCIe ethernet controller is presented to
>> the Linux host as PCI network device.
>>
>> The following block diagram gives an overview of the application.
>>              +=================================+
>>              |       Host CPU/Linux            |
>>              +=================================+
>>                         || PCIe
>>                         ||
>>         +==========================================+
>>         |           +--------------+               |
>>         |           | PCIE Endpoint|               |
>>         |           | Ethernet     |               |
>>         |           | Controller   |               |
>>         |           |   DMA        |               |
>>         |           +--------------+               |
>>         |           |   MAC        |   BCM8958X    |
>>         |           +--------------+   SoC         |
>>         |               || XGMII                   |
>>         |               ||                         |
>>         |           +--------------+               |
>>         |           | Ethernet     |               |
>>         |           | switch       |               |
>>         |           +--------------+               |
>>         |             || || || ||                  |
>>         +==========================================+
>>                       || || || || More external interfaces
>>
>> The MAC block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
>> MAC IP introduces new DMA architecture called Hyper-DMA for virtualization
>> scalability.
>>
>> Driver functionality specific to new MAC (DW25GMAC) is implemented in
>> new file dw25gmac.c.
>>
>> Management of integrated ethernet switch on this SoC is not handled by
>> the PCIe interface.
>> This SoC device has PCIe ethernet MAC directly attached to an integrated
>> ethernet switch using XGMII interface.
>>
>> v5->v6:
>>    Change summary to address comments/suggestions by Serge Semin.
>>    Patch1:
>>      Removed the comlexity of hdma mapping in previous patch series and
>>      use static DMA mapping.
>>      Renamed plat_stmmacenet_data::snps_dev_id as dev_id and moved to
>>      the beginning of the struct.
>>    Patch2:
>>      Added dw25gmac_get_hw_feature() for dw25gmac.
>>      Use static one-to-one VDMA-TC-PDMA mapping.
>>    Patch4:
>>      Remove usage of plat_stmmacenet_data::msi_*_vec variables for
>>      interrupt vector initialization.
>>      Change phy_interface type to XGMII.
>>      Cleanup unused macros.
>>
> 
> I would like to seek your guidance on how to take this patch series forward.
> Thanks to your feedback and Serge's suggestions, we made some forward
> progress on this patch series.
> Please make any suggestions to enable us to upstream driver support
> for BCM8958x.

Jitendra,
	 Have we resent this patch or got it approved ? I dont see any updates after this patch. 

> Thanks,
> Jitendra

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-02-07 18:21   ` Abhishek Chauhan (ABC)
@ 2025-02-07 23:18     ` Jitendra Vegiraju
  2025-05-28  0:04       ` Abhishek Chauhan (ABC)
  0 siblings, 1 reply; 19+ messages in thread
From: Jitendra Vegiraju @ 2025-02-07 23:18 UTC (permalink / raw)
  To: Abhishek Chauhan (ABC)
  Cc: netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, rmk+kernel, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, andrew, linux, horms,
	florian.fainelli


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Hi Abhishek,

On Fri, Feb 7, 2025 at 10:21 AM Abhishek Chauhan (ABC) <
quic_abchauha@quicinc.com> wrote:

>
>
> On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
> > Hi netdev team,
> >
> > On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
> >>
> >> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
> >>
> >> This patchset adds basic PCI ethernet device driver support for Broadcom
> >> BCM8958x Automotive Ethernet switch SoC devices.
> >>
> >
> > I would like to seek your guidance on how to take this patch series
> forward.
> > Thanks to your feedback and Serge's suggestions, we made some forward
> > progress on this patch series.
> > Please make any suggestions to enable us to upstream driver support
> > for BCM8958x.
>
> Jitendra,
>          Have we resent this patch or got it approved ? I dont see any
> updates after this patch.
>
>
Thank you for inquiring about the status of this patch.
As stmmac driver is going through a maintainer transition, we wanted to
wait until a new maintainer is identified.
We would like to send the updated patch as soon as possible.
Thanks,
Jitendra

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-02-07 23:18     ` Jitendra Vegiraju
@ 2025-05-28  0:04       ` Abhishek Chauhan (ABC)
  2025-05-28  7:58         ` Russell King (Oracle)
  2025-05-29  1:35         ` Yanteng Si
  0 siblings, 2 replies; 19+ messages in thread
From: Abhishek Chauhan (ABC) @ 2025-05-28  0:04 UTC (permalink / raw)
  To: Jitendra Vegiraju, Andrew Lunn, Russell King (Oracle)
  Cc: netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, rmk+kernel, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, andrew, linux, horms,
	florian.fainelli, Sagar Cheluvegowda



On 2/7/2025 3:18 PM, Jitendra Vegiraju wrote:
> Hi Abhishek,
> 
> On Fri, Feb 7, 2025 at 10:21 AM Abhishek Chauhan (ABC) <
> quic_abchauha@quicinc.com> wrote:
> 
>>
>>
>> On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
>>> Hi netdev team,
>>>
>>> On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
>>>>
>>>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>>>>
>>>> This patchset adds basic PCI ethernet device driver support for Broadcom
>>>> BCM8958x Automotive Ethernet switch SoC devices.
>>>>
>>>
>>> I would like to seek your guidance on how to take this patch series
>> forward.
>>> Thanks to your feedback and Serge's suggestions, we made some forward
>>> progress on this patch series.
>>> Please make any suggestions to enable us to upstream driver support
>>> for BCM8958x.
>>
>> Jitendra,
>>          Have we resent this patch or got it approved ? I dont see any
>> updates after this patch.
>>
>>
> Thank you for inquiring about the status of this patch.
> As stmmac driver is going through a maintainer transition, we wanted to
> wait until a new maintainer is identified.
> We would like to send the updated patch as soon as possible.
> Thanks,
> Jitendra
Thanks Jitendra, I am sorry but just a follow up. 

Do we know if stmmac maintainer are identified now ?

Andrew/Russell - Can you please help us ? 

Best regards
ABC

> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-05-28  0:04       ` Abhishek Chauhan (ABC)
@ 2025-05-28  7:58         ` Russell King (Oracle)
  2025-05-29  1:35         ` Yanteng Si
  1 sibling, 0 replies; 19+ messages in thread
From: Russell King (Oracle) @ 2025-05-28  7:58 UTC (permalink / raw)
  To: Abhishek Chauhan (ABC)
  Cc: Jitendra Vegiraju, Andrew Lunn, netdev, alexandre.torgue, joabreu,
	davem, edumazet, kuba, pabeni, mcoquelin.stm32,
	bcm-kernel-feedback-list, richardcochran, ast, daniel, hawk,
	john.fastabend, fancer.lancer, ahalaney, xiaolei.wang,
	rohan.g.thomas, Jianheng.Zhang, linux-kernel, linux-stm32,
	linux-arm-kernel, bpf, horms, florian.fainelli,
	Sagar Cheluvegowda

On Tue, May 27, 2025 at 05:04:52PM -0700, Abhishek Chauhan (ABC) wrote:
> Thanks Jitendra, I am sorry but just a follow up. 
> 
> Do we know if stmmac maintainer are identified now ?
> 
> Andrew/Russell - Can you please help us ? 

My mainline work is in abayence at the moment (apart from occasionally
replying to a few emails from time to time) as I have other commitments
at the moment. I still have my own patches from before the previous
merge window that I didn't get around to submitting.

Sorry, I'm not in a position to help right now.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-05-28  0:04       ` Abhishek Chauhan (ABC)
  2025-05-28  7:58         ` Russell King (Oracle)
@ 2025-05-29  1:35         ` Yanteng Si
  2025-05-29  2:56           ` Jitendra Vegiraju
  1 sibling, 1 reply; 19+ messages in thread
From: Yanteng Si @ 2025-05-29  1:35 UTC (permalink / raw)
  To: Abhishek Chauhan (ABC), Jitendra Vegiraju, Andrew Lunn,
	Russell King (Oracle)
  Cc: netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, linux, horms,
	florian.fainelli, Sagar Cheluvegowda

在 5/28/25 8:04 AM, Abhishek Chauhan (ABC) 写道:
> 
> 
> On 2/7/2025 3:18 PM, Jitendra Vegiraju wrote:
>> Hi Abhishek,
>>
>> On Fri, Feb 7, 2025 at 10:21 AM Abhishek Chauhan (ABC) <
>> quic_abchauha@quicinc.com> wrote:
>>
>>>
>>>
>>> On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
>>>> Hi netdev team,
>>>>
>>>> On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
>>>>>
>>>>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>>>>>
>>>>> This patchset adds basic PCI ethernet device driver support for Broadcom
>>>>> BCM8958x Automotive Ethernet switch SoC devices.
>>>>>
>>>>
>>>> I would like to seek your guidance on how to take this patch series
>>> forward.
>>>> Thanks to your feedback and Serge's suggestions, we made some forward
>>>> progress on this patch series.
>>>> Please make any suggestions to enable us to upstream driver support
>>>> for BCM8958x.
>>>
>>> Jitendra,
>>>           Have we resent this patch or got it approved ? I dont see any
>>> updates after this patch.
>>>
>>>
>> Thank you for inquiring about the status of this patch.
>> As stmmac driver is going through a maintainer transition, we wanted to
>> wait until a new maintainer is identified.
>> We would like to send the updated patch as soon as possible.
>> Thanks,
>> Jitendra
> Thanks Jitendra, I am sorry but just a follow up.
> 
> Do we know if stmmac maintainer are identified now ?

I'm curious why such a precondition is added？


Thanks,
Yanteng

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-05-29  1:35         ` Yanteng Si
@ 2025-05-29  2:56           ` Jitendra Vegiraju
  2025-05-29  5:14             ` Yanteng Si
  0 siblings, 1 reply; 19+ messages in thread
From: Jitendra Vegiraju @ 2025-05-29  2:56 UTC (permalink / raw)
  To: Yanteng Si
  Cc: Abhishek Chauhan (ABC), Andrew Lunn, Russell King (Oracle),
	netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, linux, horms,
	florian.fainelli, Sagar Cheluvegowda

[-- Attachment #1: Type: text/plain, Size: 2511 bytes --]

Hi Yanteng,

On Wed, May 28, 2025 at 6:36 PM Yanteng Si <si.yanteng@linux.dev> wrote:
>
> 在 5/28/25 8:04 AM, Abhishek Chauhan (ABC) 写道:
> >
> >
> > On 2/7/2025 3:18 PM, Jitendra Vegiraju wrote:
> >> Hi Abhishek,
> >>
> >> On Fri, Feb 7, 2025 at 10:21 AM Abhishek Chauhan (ABC) <
> >> quic_abchauha@quicinc.com> wrote:
> >>
> >>>
> >>>
> >>> On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
> >>>> Hi netdev team,
> >>>>
> >>>> On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
> >>>>>
> >>>>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
> >>>>>
> >>>>> This patchset adds basic PCI ethernet device driver support for Broadcom
> >>>>> BCM8958x Automotive Ethernet switch SoC devices.
> >>>>>
> >>>>
> >>>> I would like to seek your guidance on how to take this patch series
> >>> forward.
> >>>> Thanks to your feedback and Serge's suggestions, we made some forward
> >>>> progress on this patch series.
> >>>> Please make any suggestions to enable us to upstream driver support
> >>>> for BCM8958x.
> >>>
> >>> Jitendra,
> >>>           Have we resent this patch or got it approved ? I dont see any
> >>> updates after this patch.
> >>>
> >>>
> >> Thank you for inquiring about the status of this patch.
> >> As stmmac driver is going through a maintainer transition, we wanted to
> >> wait until a new maintainer is identified.
> >> We would like to send the updated patch as soon as possible.
> >> Thanks,
> >> Jitendra
> > Thanks Jitendra, I am sorry but just a follow up.
> >
> > Do we know if stmmac maintainer are identified now ?
>
> I'm curious why such a precondition is added？
>
It's not a precondition. Let me give some context.
This patch series adds support for a new Hyper DMA(HDMA) MAC from Synopsis.
Many of the netdev community members reviewed the patches at that time.
Being the module maintainer at that time, Serge took the initiative to
guide us through integrating the new MAC into the stmmac driver.
We addressed all the review comments and submitted the last patch series.
Without an official maintainer, we didn't get feedback on the last patch series.
Because of this, we wanted to wait until a new maintainer is assigned
to this module.
As Abhishek expressed in his email, it appears the HDMA MAC is
becoming more mainstream.
We are hoping to rebase the patch series and resubmit for review if
netdev team members show interest.
Thanks,
Jitendra
>
> Thanks,
> Yanteng

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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-05-29  2:56           ` Jitendra Vegiraju
@ 2025-05-29  5:14             ` Yanteng Si
  2025-05-29  5:24               ` Abhishek Chauhan (ABC)
  0 siblings, 1 reply; 19+ messages in thread
From: Yanteng Si @ 2025-05-29  5:14 UTC (permalink / raw)
  To: Jitendra Vegiraju
  Cc: Abhishek Chauhan (ABC), Andrew Lunn, Russell King (Oracle),
	netdev, alexandre.torgue, joabreu, davem, edumazet, kuba, pabeni,
	mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
	daniel, hawk, john.fastabend, fancer.lancer, ahalaney,
	xiaolei.wang, rohan.g.thomas, Jianheng.Zhang, linux-kernel,
	linux-stm32, linux-arm-kernel, bpf, linux, horms,
	florian.fainelli, Sagar Cheluvegowda


在 5/29/25 10:56 AM, Jitendra Vegiraju 写道:
> Hi Yanteng,
>
> On Wed, May 28, 2025 at 6:36 PM Yanteng Si <si.yanteng@linux.dev> wrote:
>> 在 5/28/25 8:04 AM, Abhishek Chauhan (ABC) 写道:
>>>
>>> On 2/7/2025 3:18 PM, Jitendra Vegiraju wrote:
>>>> Hi Abhishek,
>>>>
>>>> On Fri, Feb 7, 2025 at 10:21 AM Abhishek Chauhan (ABC) <
>>>> quic_abchauha@quicinc.com> wrote:
>>>>
>>>>>
>>>>> On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
>>>>>> Hi netdev team,
>>>>>>
>>>>>> On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
>>>>>>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>>>>>>>
>>>>>>> This patchset adds basic PCI ethernet device driver support for Broadcom
>>>>>>> BCM8958x Automotive Ethernet switch SoC devices.
>>>>>>>
>>>>>> I would like to seek your guidance on how to take this patch series
>>>>> forward.
>>>>>> Thanks to your feedback and Serge's suggestions, we made some forward
>>>>>> progress on this patch series.
>>>>>> Please make any suggestions to enable us to upstream driver support
>>>>>> for BCM8958x.
>>>>> Jitendra,
>>>>>            Have we resent this patch or got it approved ? I dont see any
>>>>> updates after this patch.
>>>>>
>>>>>
>>>> Thank you for inquiring about the status of this patch.
>>>> As stmmac driver is going through a maintainer transition, we wanted to
>>>> wait until a new maintainer is identified.
>>>> We would like to send the updated patch as soon as possible.
>>>> Thanks,
>>>> Jitendra
>>> Thanks Jitendra, I am sorry but just a follow up.
>>>
>>> Do we know if stmmac maintainer are identified now ?
>> I'm curious why such a precondition is added？
>>
> It's not a precondition. Let me give some context.
> This patch series adds support for a new Hyper DMA(HDMA) MAC from Synopsis.
> Many of the netdev community members reviewed the patches at that time.
> Being the module maintainer at that time, Serge took the initiative to
> guide us through integrating the new MAC into the stmmac driver.
> We addressed all the review comments and submitted the last patch series.
> Without an official maintainer, we didn't get feedback on the last patch series.
> Because of this, we wanted to wait until a new maintainer is assigned
> to this module.
> As Abhishek expressed in his email, it appears the HDMA MAC is
> becoming more mainstream.
> We are hoping to rebase the patch series and resubmit for review if
> netdev team members show interest.


https://lore.kernel.org/netdev/20241018205332.525595-1-jitendra.vegiraju@broadcom.com/

In my opinion, the precondition for waiting for a maintainer is that

the patch set has passed the review. I checked lore and did not find

any R&B tags in the patch set, which means your patch set has not

yet met the merging requirements.

Therefore, I think you can continue to push forward with this patch

set and not let it stagnate. I will take some time to review the previous

versions (which may take a while) and hope to be helpful.

Thanks,

Yanteng

> Thanks,
> Jitendra
>> Thanks,
>> Yanteng

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x
  2025-05-29  5:14             ` Yanteng Si
@ 2025-05-29  5:24               ` Abhishek Chauhan (ABC)
  0 siblings, 0 replies; 19+ messages in thread
From: Abhishek Chauhan (ABC) @ 2025-05-29  5:24 UTC (permalink / raw)
  To: Yanteng Si, Jitendra Vegiraju
  Cc: Andrew Lunn, Russell King (Oracle), netdev, alexandre.torgue,
	joabreu, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
	bcm-kernel-feedback-list, richardcochran, ast, daniel, hawk,
	john.fastabend, fancer.lancer, ahalaney, xiaolei.wang,
	rohan.g.thomas, Jianheng.Zhang, linux-kernel, linux-stm32,
	linux-arm-kernel, bpf, linux, horms, florian.fainelli,
	Sagar Cheluvegowda



On 5/28/2025 10:14 PM, Yanteng Si wrote:
> 
> 在 5/29/25 10:56 AM, Jitendra Vegiraju 写道:
>> Hi Yanteng,
>>
>> On Wed, May 28, 2025 at 6:36 PM Yanteng Si <si.yanteng@linux.dev> wrote:
>>> 在 5/28/25 8:04 AM, Abhishek Chauhan (ABC) 写道:
>>>>
>>>> On 2/7/2025 3:18 PM, Jitendra Vegiraju wrote:
>>>>> Hi Abhishek,
>>>>>
>>>>> On Fri, Feb 7, 2025 at 10:21 AM Abhishek Chauhan (ABC) <
>>>>> quic_abchauha@quicinc.com> wrote:
>>>>>
>>>>>>
>>>>>> On 11/5/2024 8:12 AM, Jitendra Vegiraju wrote:
>>>>>>> Hi netdev team,
>>>>>>>
>>>>>>> On Fri, Oct 18, 2024 at 1:53 PM <jitendra.vegiraju@broadcom.com> wrote:
>>>>>>>> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>>>>>>>>
>>>>>>>> This patchset adds basic PCI ethernet device driver support for Broadcom
>>>>>>>> BCM8958x Automotive Ethernet switch SoC devices.
>>>>>>>>
>>>>>>> I would like to seek your guidance on how to take this patch series
>>>>>> forward.
>>>>>>> Thanks to your feedback and Serge's suggestions, we made some forward
>>>>>>> progress on this patch series.
>>>>>>> Please make any suggestions to enable us to upstream driver support
>>>>>>> for BCM8958x.
>>>>>> Jitendra,
>>>>>>            Have we resent this patch or got it approved ? I dont see any
>>>>>> updates after this patch.
>>>>>>
>>>>>>
>>>>> Thank you for inquiring about the status of this patch.
>>>>> As stmmac driver is going through a maintainer transition, we wanted to
>>>>> wait until a new maintainer is identified.
>>>>> We would like to send the updated patch as soon as possible.
>>>>> Thanks,
>>>>> Jitendra
>>>> Thanks Jitendra, I am sorry but just a follow up.
>>>>
>>>> Do we know if stmmac maintainer are identified now ?
>>> I'm curious why such a precondition is added？
>>>
>> It's not a precondition. Let me give some context.
>> This patch series adds support for a new Hyper DMA(HDMA) MAC from Synopsis.
>> Many of the netdev community members reviewed the patches at that time.
>> Being the module maintainer at that time, Serge took the initiative to
>> guide us through integrating the new MAC into the stmmac driver.
>> We addressed all the review comments and submitted the last patch series.
>> Without an official maintainer, we didn't get feedback on the last patch series.
>> Because of this, we wanted to wait until a new maintainer is assigned
>> to this module.
>> As Abhishek expressed in his email, it appears the HDMA MAC is
>> becoming more mainstream.
>> We are hoping to rebase the patch series and resubmit for review if
>> netdev team members show interest.
> 
> 
> https://lore.kernel.org/netdev/20241018205332.525595-1-jitendra.vegiraju@broadcom.com/
> 
> In my opinion, the precondition for waiting for a maintainer is that
> 
> the patch set has passed the review. I checked lore and did not find
> 
> any R&B tags in the patch set, which means your patch set has not
> 
> yet met the merging requirements.
> 
> Therefore, I think you can continue to push forward with this patch
> 
> set and not let it stagnate. I will take some time to review the previous
> 
> versions (which may take a while) and hope to be helpful.
> 
> Thanks,
> 
> Yanteng
> 
I will review the patch in the coming few days as well. As this patch also helps Qualcomm to develop the 
HDMA arch for 25XGMAC EMAC controller. 
This patch is validated/verfied/tested on Qualcomm platform devices which are not PCIE based. 
>> Thanks,
>> Jitendra
>>> Thanks,
>>> Yanteng

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2025-05-29  5:25 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-18 20:53 [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
2024-10-18 20:53 ` [PATCH net-next v6 1/5] net: stmmac: Add snps_id, dev_id to struct plat_stmmacenet_data jitendra.vegiraju
2024-10-18 20:53 ` [PATCH net-next v6 2/5] net: stmmac: Add basic dw25gmac support in stmmac core jitendra.vegiraju
2024-10-24  1:35   ` Abhishek Chauhan (ABC)
2024-10-24  5:21     ` Abhishek Chauhan (ABC)
2024-10-18 20:53 ` [PATCH net-next v6 3/5] net: stmmac: Integrate dw25gmac into stmmac hwif handling jitendra.vegiraju
2024-10-18 20:53 ` [PATCH net-next v6 4/5] net: stmmac: Add PCI driver support for BCM8958x jitendra.vegiraju
2024-10-18 20:53 ` [PATCH net-next v6 5/5] net: stmmac: Add BCM8958x driver to build system jitendra.vegiraju
2024-10-21 11:05 ` [PATCH net-next v6 0/5] net: stmmac: Add PCI driver support for BCM8958x Serge Semin
2024-10-21 16:01   ` Jitendra Vegiraju
2024-11-05 16:12 ` Jitendra Vegiraju
2025-02-07 18:21   ` Abhishek Chauhan (ABC)
2025-02-07 23:18     ` Jitendra Vegiraju
2025-05-28  0:04       ` Abhishek Chauhan (ABC)
2025-05-28  7:58         ` Russell King (Oracle)
2025-05-29  1:35         ` Yanteng Si
2025-05-29  2:56           ` Jitendra Vegiraju
2025-05-29  5:14             ` Yanteng Si
2025-05-29  5:24               ` Abhishek Chauhan (ABC)

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