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Sat, 07 Jun 2025 04:00:38 -0700 (PDT) Received: from geday ([2804:7f2:800b:2bc9::dead:c001]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7482b083abcsm2642030b3a.92.2025.06.07.04.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 04:00:37 -0700 (PDT) Date: Sat, 7 Jun 2025 08:00:23 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 0/4] Quality Improvements for Rockchip-IP PCIe Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe TEST_WRITE. Geraldo Nascimento (4): PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 PCI: rockchip-host: Set Target Link Speed before retraining phy: rockchip-pcie: enable all four lanes phy: rockchip-pcie: adjust read mask and write strobe disable drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ drivers/pci/controller/pcie-rockchip.h | 3 +++ drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++------- 3 files changed, 16 insertions(+), 7 deletions(-) -- 2.49.0