Re: [RFC PATCH 0/4] Quality Improvements for Rockchip-IP PCIe

Heiko Stuebner
2025-06-09T08:51:07Z

Hi Geraldo,

Am Samstag, 7. Juni 2025, 13:00:23 Mitteleuropäische Sommerzeit schrieb Geraldo Nascimento:
> During a 30-day debugging-run fighting quirky PCIe devices on RK3399
> some quality improvements began to take form and this is my attempt
> at upstreaming it. It will ensure maximum chance of retraining to Gen2
> 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY
> they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0]
> without risk of locking up kernel like with present broken async
> strobe TEST_WRITE.

could you check your settings for sending patches please?

The individual patches of this series did not get "in-reply-to" headers
that would point to this cover-letter. Instead each mail of this
series stands on its own, preventing mail clients from creating a
threaded display of the series.

git-send-email normally does create these needed headers on its own,
so could you check if you have some option enabled that prevents this?

Thanks a lot
Heiko

>
> Geraldo Nascimento (4):
> PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
> PCI: rockchip-host: Set Target Link Speed before retraining
> phy: rockchip-pcie: enable all four lanes
> phy: rockchip-pcie: adjust read mask and write strobe disable
>
> drivers/pci/controller/pcie-rockchip-host.c | 4 ++++
> drivers/pci/controller/pcie-rockchip.h | 3 +++
> drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++-------
> 3 files changed, 16 insertions(+), 7 deletions(-)
>
>