Re: [PATCH v4 1/2] PCI: Configure root port MPS during host probing

Manivannan Sadhasivam
2025-06-19T12:45:38Z

On Fri, Jun 13, 2025 at 11:31:01PM +0800, Hans Zhang wrote:
>
>
> On 2025/6/13 19:52, Niklas Cassel wrote:
> > On Fri, Jun 13, 2025 at 12:08:31PM +0530, Manivannan Sadhasivam wrote:
> > > On Sat, May 10, 2025 at 11:56:06PM +0800, Hans Zhang wrote:
> > > > Current PCIe initialization logic may leave root ports operating with
> > > > non-optimal Maximum Payload Size (MPS) settings. While downstream device
> > > > configuration is handled during bus enumeration, root port MPS values
> > > > inherited from firmware or hardware defaults might not utilize the full
> > > > capabilities supported by the controller hardware. This can result is
> > > > uboptimal data transfer efficiency across the PCIe hierarchy.
> > > >
> > > > During host controller probing phase, when PCIe bus tuning is enabled,
> > > > the implementation now configures root port MPS settings to their
> > > > hardware-supported maximum values. By iterating through bridge devices
> > > > under the root bus and identifying PCIe root ports, each port's MPS is
> > > > set to 128 << pcie_mpss to match the device's maximum supported payload
> > > > size.
> > >
> > > I don't think the above statement is accurate. This patch is not iterating
> > > through the bridges and you cannot identify root ports using that. What this
> > > patch does is, it checks whether the device is root port or not and if it is,
> > > then it sets the MPS to MPSS (hw maximum) if PCIE_BUS_TUNE_OFF is not set.
> >
> > Correct.
> > Later, when the bus is walked, if any downstream device does not support
> > the MPS value currently configured in the root port, pci_configure_mps()
> > will reduce the MPS in the root port to the max supported by the downstream
> > device.
> >
> > So even we start off by setting MPS in the root port to the max supported
> > by the root port, it might get reduced later on.
> >
> >
>
> Dear Mani and Niklas,
>
> Is it okay to modify the commit message as follows? The last paragraph
> remains unchanged.
>
>
>
> Current PCIe initialization logic may leave root ports operating with
> non-optimal Maximum Payload Size (MPS) settings. While downstream device
> configuration is handled during bus enumeration, root port MPS values
> inherited from firmware or hardware defaults might not utilize the full
> capabilities supported by the controller hardware. This can result in
> suboptimal data transfer efficiency across the PCIe hierarchy.
>
> During host controller probing phase, when PCIe bus tuning is enabled,
> the implementation now configures root port MPS settings to their
> hardware-supported maximum values. Specifically, when configuring the MPS
> for a PCIe device, if the device is a root port and the bus tuning is not
> disabled (PCIE_BUS_TUNE_OFF), the MPS is set to 128 << dev->pcie_mpss to
> match the device's maximum supported payload size. The Max Read Request

s/device/Root Port

> Size (MRRS) is subsequently adjusted through existing companion logic to
> maintain compatibility with PCIe specifications.
>
> Note that this initial setting of the root port MPS to the maximum might
> be reduced later during the enumeration of downstream devices if any of
> those devices do not support the maximum MPS of the root port.
>

Rest LGTM!

- Mani

--
மணிவண்ணன் சதாசிவம்