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Fri, 13 Jun 2025 14:01:40 -0700 (PDT) Received: from geday ([2804:7f2:800b:84a2::dead:c001]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-748900051a6sm2111176b3a.42.2025.06.13.14.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 14:01:39 -0700 (PDT) Date: Fri, 13 Jun 2025 18:01:34 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RESEND RFC PATCH v4 1/5] PCI: rockchip: Use standard PCIe defines Message-ID: References: <20250613205023.GA975137@bhelgaas> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250613205023.GA975137@bhelgaas> On Fri, Jun 13, 2025 at 03:50:23PM -0500, Bjorn Helgaas wrote: > I don't have access to any of these TRMs, so I only know what's in the > driver. > They are not under NDA and can be obtained though Rockchip's official site: https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf > When you say "without fear", are you saying there's a way to do that > 32-bit write such that the LNKSTA bits are discarded by the hardware? > Or just that the hardware forces us to accept this potential status > register corruption? I meant to say those registers themselves are defined in TRM as 32 bits. > > Is this something that could be written using the config access path? > I guess probably not, based on this: > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip-host.c?id=v6.15#n141 > That certainly looks frightening. > Bjorn