From: Johan Hovold <johan@kernel.org>
To: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com,
mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org,
kishon@kernel.org, neil.armstrong@linaro.org,
abel.vesa@linaro.org, kw@linux.com,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com,
quic_krichai@quicinc.com, quic_vbadigan@quicinc.com
Subject: Re: [PATCH v6 1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
Date: Fri, 27 Jun 2025 11:22:06 +0200 [thread overview]
Message-ID: <aF5ivn2uNTqOPrmR@hovoldconsulting.com> (raw)
In-Reply-To: <20250625063213.1416442-2-quic_ziyuzhan@quicinc.com>
On Wed, Jun 25, 2025 at 02:32:11PM +0800, Ziyue Zhang wrote:
> QCS615 pcie phy only use 5 clocks, which are aux, cfg_ahb, ref,
> ref_gen, pipe. So move "qcom,qcs615-qmp-gen3x1-pcie-phy" compatible
> from 6 clocks' list to 5 clocks' list.
Please add a Fixes tag pointing out the commit that erroneously
described the PHY as requiring six clocks.
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Johan
next prev parent reply other threads:[~2025-06-27 9:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-25 6:32 [PATCH v6 0/3] pci: qcom: Add QCS615 PCIe support Ziyue Zhang
2025-06-25 6:32 ` [PATCH v6 1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615 Ziyue Zhang
2025-06-27 9:22 ` Johan Hovold [this message]
2025-06-25 6:32 ` [PATCH v6 2/3] arm64: dts: qcom: qcs615: enable pcie Ziyue Zhang
2025-06-25 6:32 ` [PATCH v6 3/3] arm64: dts: qcom: qcs615-ride: Enable PCIe interface Ziyue Zhang
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