From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>,
Sascha Bischoff <sascha.bischoff@arm.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Timothy Hayes <timothy.hayes@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
Peter Maydell <peter.maydell@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Jiri Slaby <jirislaby@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 24/27] irqchip/gic-v5: Add GICv5 ITS support
Date: Wed, 18 Jun 2025 21:56:54 +0200 [thread overview]
Message-ID: <aFMaBlByS8xPq6kc@lpieralisi> (raw)
In-Reply-To: <20250618-gicv5-host-v5-24-d9e622ac5539@kernel.org>
On Wed, Jun 18, 2025 at 12:17:39PM +0200, Lorenzo Pieralisi wrote:
[...]
> +static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
> + int nvec, msi_alloc_info_t *info)
> +{
> + struct msi_domain_info *msi_info;
> + struct device_node *msi_node;
> + struct pci_dev *pdev;
> + phys_addr_t pa;
> + int ret;
> +
> + if (!dev_is_pci(dev))
> + return -EINVAL;
> +
> + pdev = to_pci_dev(dev);
> +
> + msi_node = pci_msi_get_device_msi_ctlr_node(pdev);
> + if (!msi_node)
> + return -ENODEV;
> +
> + ret = its_translate_frame_address(msi_node, &pa);
> + if (ret)
> + return -ENODEV;
> +
> + of_node_put(msi_node);
> +
> + /* ITS specific DeviceID */
> + info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain->parent, pdev);
Heads-up: it turned out I was too optimistic and reusing
pci_msi_domain_get_msi_rid()
on GICv5 does not work (or better it works incorrectly).
It calls (for DT) of_msi_map_id() with the IRQ domain of_node (why, I am
not sure but for GICv3 it works because the phandle in the msi-map and
the IRQ domain of_node are equivalent). This does _not_ work on GICv5,
I failed to spot it because in of_msi_map_id() if the IRQ domain of_node
and msi-map phandle do not match a 1:1 translation is carried out, which
ironically is what the RID<->DID translation looks like in the test
platform. Sigh.
I have already patched the code to augment:
pci_msi_get_device_msi_ctlr_node()
so that it grabs the msi-controller of_node pointer in msi-map AND maps the
RID->DID (and to be honest that's what I should have done but I wanted to
reuse pci_msi_domain_get_msi_rid(), it does not work for GICv5 unless I
change it but I fear I could break platforms, we don't fix what it is not
broken).
Long story short: apologies, I missed this snag for the reasons above, I
will update it for v6.
Thanks,
Lorenzo
next prev parent reply other threads:[~2025-06-18 19:57 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 10:17 [PATCH v5 00/27] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 01/27] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-06-18 18:52 ` Rob Herring (Arm)
2025-06-18 10:17 ` [PATCH v5 02/27] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 03/27] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 04/27] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 05/27] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 06/27] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 07/27] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 08/27] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 09/27] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 10/27] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 11/27] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 12/27] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 13/27] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 14/27] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 15/27] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 16/27] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 17/27] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 18/27] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-06-25 18:53 ` Marc Zyngier
2025-06-18 10:17 ` [PATCH v5 19/27] arm64: Add support for GICv5 GSB barriers Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 20/27] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 21/27] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 22/27] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 23/27] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 24/27] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-06-18 19:56 ` Lorenzo Pieralisi [this message]
2025-06-20 19:18 ` Thomas Gleixner
2025-06-23 7:43 ` Lorenzo Pieralisi
2025-06-23 9:26 ` Lorenzo Pieralisi
2025-06-23 19:04 ` Thomas Gleixner
2025-06-18 10:17 ` [PATCH v5 25/27] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 26/27] docs: arm64: gic-v5: Document booting requirements for GICv5 Lorenzo Pieralisi
2025-06-18 10:17 ` [PATCH v5 27/27] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
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