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Wed, 09 Jul 2025 07:41:31 -0700 (PDT) Date: Wed, 9 Jul 2025 07:41:30 -0700 In-Reply-To: <20250709033242.267892-1-Neeraj.Upadhyay@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250709033242.267892-1-Neeraj.Upadhyay@amd.com> Message-ID: Subject: Re: [RFC PATCH v8 00/35] AMD: Add Secure AVIC Guest Support From: Sean Christopherson To: Neeraj Upadhyay Cc: linux-kernel@vger.kernel.org, bp@alien8.de, tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com, Thomas.Lendacky@amd.com, nikunj@amd.com, Santosh.Shukla@amd.com, Vasant.Hegde@amd.com, Suravee.Suthikulpanit@amd.com, David.Kaplan@amd.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, pbonzini@redhat.com, kvm@vger.kernel.org, kirill.shutemov@linux.intel.com, huibo.wang@amd.com, naveen.rao@amd.com, kai.huang@intel.com Content-Type: text/plain; charset="us-ascii" On Wed, Jul 09, 2025, Neeraj Upadhyay wrote: > Kishon Vijay Abraham I (2): > x86/sev: Initialize VGIF for secondary VCPUs for Secure AVIC > x86/sev: Enable NMI support for Secure AVIC > > Neeraj Upadhyay (32): > KVM: x86: Open code setting/clearing of bits in the ISR > KVM: x86: Remove redundant parentheses around 'bitmap' > KVM: x86: Rename VEC_POS/REG_POS macro usages > KVM: x86: Change lapic regs base address to void pointer > KVM: x86: Rename find_highest_vector() > KVM: x86: Rename lapic get/set_reg() helpers > KVM: x86: Rename lapic get/set_reg64() helpers > KVM: x86: Rename lapic set/clear vector helpers > x86/apic: KVM: Move apic_find_highest_vector() to a common header > x86/apic: KVM: Move lapic get/set helpers to common code > x86/apic: KVM: Move lapic set/clear_vector() helpers to common code > x86/apic: KVM: Move apic_test)vector() to common code > x86/apic: Rename 'reg_off' to 'reg' > x86/apic: Unionize apic regs for 32bit/64bit access w/o type casting > x86/apic: Simplify bitwise operations on apic bitmap > x86/apic: Move apic_update_irq_cfg() calls to apic_update_vector() > x86/apic: Add new driver for Secure AVIC > x86/apic: Initialize Secure AVIC APIC backing page > x86/apic: Populate .read()/.write() callbacks of Secure AVIC driver > x86/apic: Initialize APIC ID for Secure AVIC > x86/apic: Add update_vector() callback for apic drivers > x86/apic: Add update_vector() callback for Secure AVIC > x86/apic: Add support to send IPI for Secure AVIC > x86/apic: Support LAPIC timer for Secure AVIC > x86/apic: Add support to send NMI IPI for Secure AVIC > x86/apic: Allow NMI to be injected from hypervisor for Secure AVIC > x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests > x86/apic: Handle EOI writes for Secure AVIC guests > x86/apic: Add kexec support for Secure AVIC > x86/apic: Enable Secure AVIC in Control MSR > x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC > guests > x86/sev: Indicate SEV-SNP guest supports Secure AVIC > > Sean Christopherson (1): > x86/apic: KVM: Deduplicate APIC vector => register+bit math Boris, do you anticipate taking this entire series for 6.17? If not, I'd be more than happy to grab all of the KVM => x86/apic renames and code movement for 6.17, e.g. to avoid complications if a conflicting KVM change comes along. I can throw them in a dedicated topic branch so that you could ingest the dependency prior to 6.17-rc1 if necessary. I.e. these: x86/apic: Rename 'reg_off' to 'reg' x86/apic: KVM: Move apic_test)vector() to common code x86/apic: KVM: Move lapic set/clear_vector() helpers to common code x86/apic: KVM: Move lapic get/set helpers to common code x86/apic: KVM: Move apic_find_highest_vector() to a common header KVM: x86: Rename lapic set/clear vector helpers KVM: x86: Rename lapic get/set_reg64() helpers KVM: x86: Rename lapic get/set_reg() helpers KVM: x86: Rename find_highest_vector() KVM: x86: Change lapic regs base address to void pointer KVM: x86: Rename VEC_POS/REG_POS macro usages x86/apic: KVM: Deduplicate APIC vector => register+bit math KVM: x86: Remove redundant parentheses around 'bitmap' KVM: x86: Open code setting/clearing of bits in the ISR