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AJvYcCUIRqS8iL0wBDwfNVRJIQqXWeqFPrUab2lqFkSxUokFS6THPnh0CMFawFKxrpsNgOD5xMYHauVsnDodQeM=@vger.kernel.org X-Gm-Message-State: AOJu0YzSulGVLT7HkzNSmKWJblNf7vwv0kdeb6flt/AlbKsnd07JeZ3h nB0YEot5VgckYX0FBxP9KXlbymZSjODVfBMsyManujfsLAj2YnC6P0EjLj2DvbRNBzlsdncsOCP 09CGPgA== X-Google-Smtp-Source: AGHT+IFl8zMk4n4kKwZdLDcVRgIXGtT2XaLzjhr0sN/pKm4EFVOSPvZMjw56qXhYU9AsX5p7+6HZjthUz/0= X-Received: from pgbee1.prod.google.com ([2002:a05:6a02:4581:b0:b1f:fd39:8314]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:12c7:b0:21f:51ea:5c57 with SMTP id adf61e73a8af0-22b437de321mr627011637.16.1751919960279; Mon, 07 Jul 2025 13:26:00 -0700 (PDT) Date: Mon, 7 Jul 2025 13:25:59 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250626125720.3132623-1-alexandre.chartre@oracle.com> <67bd4e2f-24a8-49d8-80af-feaca6926e45@intel.com> <61df5e77-dfc4-4189-a86d-f1b2cabcac88@oracle.com> Message-ID: Subject: Re: [PATCH] kvm/x86: ARCH_CAPABILITIES should not be advertised on AMD From: Sean Christopherson To: Konrad Rzeszutek Wilk Cc: Alexandre Chartre , Linus Torvalds , Xiaoyao Li , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, pbonzini@redhat.com, x86@kernel.org, boris.ostrovsky@oracle.com, Jim Mattson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Fri, Jun 27, 2025, Konrad Rzeszutek Wilk wrote: > On Fri, Jun 27, 2025 at 08:23:52AM +0200, Alexandre Chartre wrote: > >=20 > > On 6/27/25 07:41, Xiaoyao Li wrote: > > > On 6/26/2025 10:02 PM, Sean Christopherson wrote: > > > > +Jim > > > >=20 > > > > For the scope, "KVM: x86:" > > > >=20 > > > > On Thu, Jun 26, 2025, Alexandre Chartre wrote: > > > > > KVM emulates the ARCH_CAPABILITIES on x86 for both vmx and svm. > > > > > However the IA32_ARCH_CAPABILITIES MSR is an Intel-specific MSR > > > > > so it makes no sense to emulate it on AMD. > > > > >=20 > > > > > The AMD documentation specifies that this MSR is not defined on > > > > > the AMD architecture. So emulating this MSR on AMD can even cause > > > > > issues (like Windows BSOD) as the guest OS might not expect this > > > > > MSR to exist on such architecture. > > > > >=20 > > > > > Signed-off-by: Alexandre Chartre > > > > > --- > > > > >=20 > > > > > A similar patch was submitted some years ago but it looks like it= felt > > > > > through the cracks: > > > > > https://lore.kernel.org/kvm/20190307093143.77182-1- xiaoyao.li@li= nux.intel.com/ > > > > It didn't fall through the cracks, we deliberately elected to emula= te the MSR in > > > > common code so that KVM's advertised CPUID support would match KVM'= s emulation. > > > >=20 > > > > =C2=A0=C2=A0 On Thu, 2019-03-07 at 19:15 +0100, Paolo Bonzini wrote= : > > > > =C2=A0=C2=A0 > On 07/03/19 18:37, Sean Christopherson wrote: > > > > =C2=A0=C2=A0 > > On Thu, Mar 07, 2019 at 05:31:43PM +0800, Xiaoyao = Li wrote: > > > > =C2=A0=C2=A0 > > > At present, we report F(ARCH_CAPABILITIES) for x= 86 arch(both vmx and svm) > > > > =C2=A0=C2=A0 > > > unconditionally, but we only emulate this MSR in= vmx. It will cause #GP > > > > =C2=A0=C2=A0 > > > while guest kernel rdmsr(MSR_IA32_ARCH_CAPABILIT= IES) in an AMD host. > > > > =C2=A0=C2=A0 > > > > > > > =C2=A0=C2=A0 > > > Since MSR IA32_ARCH_CAPABILITIES is an intel-spe= cific MSR, it makes no > > > > =C2=A0=C2=A0 > > > sense to emulate it in svm. Thus this patch choo= ses to only emulate it > > > > =C2=A0=C2=A0 > > > for vmx, and moves the related handling to vmx r= elated files. > > > > =C2=A0=C2=A0 > > > > > > =C2=A0=C2=A0 > > What about emulating the MSR on an AMD host for te= sting purpsoes?=C2=A0 It > > > > =C2=A0=C2=A0 > > might be a useful way for someone without Intel ha= rdware to test spectre > > > > =C2=A0=C2=A0 > > related flows. > > > > =C2=A0=C2=A0 > > > > > > =C2=A0=C2=A0 > > In other words, an alternative to restricting emul= ation of the MSR to > > > > =C2=A0=C2=A0 > > Intel CPUS would be to move MSR_IA32_ARCH_CAPABILI= TIES handling into > > > > =C2=A0=C2=A0 > > kvm_{get,set}_msr_common().=C2=A0 Guest access to = MSR_IA32_ARCH_CAPABILITIES > > > > =C2=A0=C2=A0 > > is gated by X86_FEATURE_ARCH_CAPABILITIES in the g= uest's CPUID, e.g. > > > > =C2=A0=C2=A0 > > RDMSR will naturally #GP fault if userspace passes= through the host's > > > > =C2=A0=C2=A0 > > CPUID on a non-Intel system. > > > > =C2=A0=C2=A0 > > > > > =C2=A0=C2=A0 > This is also better because it wouldn't change the g= uest ABI for AMD > > > > =C2=A0=C2=A0 > processors.=C2=A0 Dropping CPUID flags is generally = not a good idea. > > > > =C2=A0=C2=A0 > > > > > =C2=A0=C2=A0 > Paolo > > > >=20 > > > > I don't necessarily disagree about emulating ARCH_CAPABILITIES bein= g pointless, > > > > but Paolo's point about not changing ABI for existing setups still = stands.=C2=A0 This > > > > has been KVM's behavior for 6 years (since commit 0cf9135b773b ("KV= M: x86: Emulate > > > > MSR_IA32_ARCH_CAPABILITIES on AMD hosts"); 7 years, if we go back t= o when KVM > > > > enumerated support without emulating the MSR (commit 1eaafe91a0df (= "kvm: x86: > > > > IA32_ARCH_CAPABILITIES is always supported"). > > > >=20 > > > > And it's not like KVM is forcing userspace to enumerate support for > > > > ARCH_CAPABILITIES, e.g. QEMU's named AMD configs don't enumerate su= pport.=C2=A0 So > > > > while I completely agree KVM's behavior is odd and annoying for use= rspace to deal > > > > with, this is probably something that should be addressed in usersp= ace. > > > >=20 > > > > > I am resurecting this change because some recent Windows updates = (like OS Build > > > > > 26100.4351) crashes on AMD KVM guests (BSOD with Stop code: UNSUP= PORTED PROCESSOR) > > > > > just because the ARCH_CAPABILITIES is available. > > >=20 > > > Isn't it the Windows bugs? I think it is incorrect to assume AMD will= never implement ARCH_CAPABILITIES. > > >=20 > >=20 > > Yes, although on one hand they are just following the current AMD speci= fication which > > says that ARCH_CAPABILITIES is not defined on AMD cpus; but on the othe= r hand they are > > breaking a 6+ years behavior. So it might be nice if we could prevent s= uch an issue in > > the future. >=20 > Hi Sean, >=20 > Part of the virtualization stack is to lie accurately and in this case > KVM is doing it incorrectly.=20 No, KVM isn't doing anything "incorrectly". The ioctl in question, KVM_GET_SUPPORTED_CPUID, advertises what *KVM* supports. The CPUID model t= hat is configured for and presented to the guest is fully controlled by userspa= ce, i.e. by QEMU. And relative to what KVM is advertising, KVM's behavior is correct. Prior = to commit 0cf9135b773b, KVM was indeed buggy, because KVM didn't emulate a fea= ture that was advertised to userspace. But that hasn't been the case for 6+ yea= rs. Even if KVM were explicitly setting guest CPUID, KVM's behavior _still_ wou= ldn't be incorrect, because it wouldn't violate AMD's architecture. Per AMD's AP= M, software cannot assume reserved CPUID bits are '0': All bit positions that are not defined as fields are reserved. The value = of bits within reserved ranges cannot be relied upon to be zero. Software mu= st mask off all reserved bits in the return value prior to making any value comparisons of represented information. > Not fixing it b/c of it being for 7 years in and being part of an ABI but > saying it should be fixed in QEMU sounds like you agree technically, but = are > constrained by a policy. I'm not constrained by policy, I'm weighing the risk vs. reward of changing= KVM's ABI to remedy a problem that affects exactly one configuration in one VMM, = is relatively straightforward to address in said VMM, and has already been fix= ed in the affected guest kernel (because as above, QEMU's behavior isn't a violat= ion of AMD's architecture).