* [PATCH v2 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller
2025-07-23 11:08 [PATCH 0/4] Enable cpufreq for IPQ5424 Varadarajan Narayanan
@ 2025-07-23 11:08 ` Varadarajan Narayanan
2025-07-24 8:14 ` Krzysztof Kozlowski
2025-07-23 11:08 ` [PATCH v2 2/4] clk: qcom: apss-ipq5424: " Varadarajan Narayanan
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Varadarajan Narayanan @ 2025-07-23 11:08 UTC (permalink / raw)
To: andersson, mturquette, sboyd, robh, krzk+dt, conor+dt,
konradybcio, rafael, viresh.kumar, ilia.lin, djakov,
quic_srichara, quic_mdalam, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-pm
Cc: Varadarajan Narayanan
From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Add #interconnect-cells to help enable L3 pll as ICC clock
Add master/slave ids
---
.../bindings/clock/qcom,ipq5424-apss-clk.yaml | 61 +++++++++++++++++++
include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
.../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
3 files changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
new file mode 100644
index 000000000000..abb9eb78d271
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APSS IPQ5424 Clock Controller
+
+maintainers:
+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>
+ - Md Sadre Alam <quic_mdalam@quicinc.com>
+
+description: |
+ The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
+ The RCG and PLL have a separate register space from the GCC.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5424-apss-clk
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference to the XO clock.
+ - description: Reference to the GPLL0 clock.
+
+ clock-names:
+ items:
+ - const: xo
+ - const: gpll0
+
+ '#clock-cells':
+ const: 1
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#interconnect-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+
+ apss_clk: apss-clock@fa80000 {
+ compatible = "qcom,ipq5424-apss-clk";
+ reg = <0x0fa80000 0x20000>;
+ clocks = <&xo_board>, <&gcc GPLL0>;
+ clock-names = "xo", "gpll0";
+ #clock-cells = <1>;
+ #interconnect-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
index 77b6e05492e2..0bb41e5efdef 100644
--- a/include/dt-bindings/clock/qcom,apss-ipq.h
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -8,5 +8,11 @@
#define APCS_ALIAS0_CLK_SRC 0
#define APCS_ALIAS0_CORE_CLK 1
+#define APSS_PLL_EARLY 2
+#define APSS_SILVER_CLK_SRC 3
+#define APSS_SILVER_CORE_CLK 4
+#define L3_PLL 5
+#define L3_CLK_SRC 6
+#define L3_CORE_CLK 7
#endif
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
index a770356112ee..afd7e0683a24 100644
--- a/include/dt-bindings/interconnect/qcom,ipq5424.h
+++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -21,4 +21,7 @@
#define MASTER_CNOC_USB 16
#define SLAVE_CNOC_USB 17
+#define MASTER_CPU 0
+#define SLAVE_L3 1
+
#endif /* INTERCONNECT_QCOM_IPQ5424_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller
2025-07-23 11:08 [PATCH 0/4] Enable cpufreq for IPQ5424 Varadarajan Narayanan
2025-07-23 11:08 ` [PATCH v2 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller Varadarajan Narayanan
@ 2025-07-23 11:08 ` Varadarajan Narayanan
2025-07-23 13:09 ` Konrad Dybcio
2025-07-23 11:08 ` [PATCH v2 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424 Varadarajan Narayanan
2025-07-23 11:08 ` [PATCH v2 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq Varadarajan Narayanan
3 siblings, 1 reply; 9+ messages in thread
From: Varadarajan Narayanan @ 2025-07-23 11:08 UTC (permalink / raw)
To: andersson, mturquette, sboyd, robh, krzk+dt, conor+dt,
konradybcio, rafael, viresh.kumar, ilia.lin, djakov,
quic_srichara, quic_mdalam, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-pm
Cc: Varadarajan Narayanan
From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support.
Add support for the APSS PLL, RCG and clock enable for ipq5424.
The PLL, RCG register space are clubbed. Hence adding new APSS driver
for both PLL and RCG/CBC control. Also the L3 cache has a separate pll
and needs to be scaled along with the CPU and is modeled as an ICC clock.
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Removed clock notifier, moved L3 pll to icc-clk, used existing
alpha pll structure ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Model L3 pll as ICC clock and add relevant structures
Use CLK_ALPHA_PLL_TYPE_HUAYRA_2290 register offsets instead
of duplicate ipq5424_pll_offsets definition.
Inline clock rates.
Fix MODULE_LICENSE
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq5424.c | 282 ++++++++++++++++++++++++++++++++
3 files changed, 290 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq5424.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 6cb6cd3e1778..dae89599a40e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -208,6 +208,13 @@ config IPQ_CMN_PLL
Say Y or M if you want to support CMN PLL clock on the IPQ
based devices.
+config IPQ_APSS_5424
+ tristate "IPQ APSS Clock Controller"
+ help
+ Support for APSS Clock controller on Qualcom IPQ5424 platform.
+ Say Y if you want to support CPU frequency scaling on ipq based
+ devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index ddb7e06fae40..98de55eb6402 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
obj-$(CONFIG_CLK_X1P42100_GPUCC) += gpucc-x1p42100.o
obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+obj-$(CONFIG_IPQ_APSS_5424) += apss-ipq5424.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
diff --git a/drivers/clk/qcom/apss-ipq5424.c b/drivers/clk/qcom/apss-ipq5424.c
new file mode 100644
index 000000000000..7ce1e169b9a1
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq5424.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/interconnect/qcom,ipq5424.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_APSS_PLL_EARLY,
+ P_L3_PLL,
+};
+
+struct apss_clk {
+ struct notifier_block cpu_clk_notifier;
+ struct clk_hw *hw;
+ struct device *dev;
+ struct clk *l3_clk;
+};
+
+static struct clk_alpha_pll ipq5424_apss_pll = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apss_pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xo-board-clk",
+ },
+ .parent_names = (const char *[]){ "xo-board-clk"},
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data parents_apss_silver_clk_src[] = {
+ { .fw_name = "xo-board-clk" },
+ { .fw_name = "gpll0" },
+ { .hw = &ipq5424_apss_pll.clkr.hw },
+};
+
+static const struct parent_map parents_apss_silver_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 4 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+static const struct freq_tbl ftbl_apss_clk_src[] = {
+ F(800000000, P_GPLL0, 1, 0, 0),
+ F(1416000000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(1800000000, P_APSS_PLL_EARLY, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 apss_silver_clk_src = {
+ .cmd_rcgr = 0x0080,
+ .freq_tbl = ftbl_apss_clk_src,
+ .hid_width = 5,
+ .parent_map = parents_apss_silver_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apss_silver_clk_src",
+ .parent_data = parents_apss_silver_clk_src,
+ .num_parents = ARRAY_SIZE(parents_apss_silver_clk_src),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apss_silver_core_clk = {
+ .halt_reg = 0x008c,
+ .clkr = {
+ .enable_reg = 0x008c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apss_silver_core_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &apss_silver_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll ipq5424_l3_pll = {
+ .offset = 0x10000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "l3_pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xo-board-clk",
+ },
+ .parent_names = (const char *[]){ "xo-board-clk"},
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data parents_l3_clk_src[] = {
+ { .fw_name = "xo-board-clk" },
+ { .fw_name = "gpll0" },
+ { .hw = &ipq5424_l3_pll.clkr.hw },
+};
+
+static const struct parent_map parents_l3_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 4 },
+ { P_L3_PLL, 5 },
+};
+
+static const struct freq_tbl ftbl_l3_clk_src[] = {
+ F(800000000, P_GPLL0, 1, 0, 0),
+ F(984000000, P_L3_PLL, 1, 0, 0),
+ F(1272000000, P_L3_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 l3_clk_src = {
+ .cmd_rcgr = 0x10080,
+ .freq_tbl = ftbl_l3_clk_src,
+ .hid_width = 5,
+ .parent_map = parents_l3_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "l3_clk_src",
+ .parent_data = parents_l3_clk_src,
+ .num_parents = ARRAY_SIZE(parents_l3_clk_src),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch l3_core_clk = {
+ .halt_reg = 0x1008c,
+ .clkr = {
+ .enable_reg = 0x1008c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "l3_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &l3_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static const struct regmap_config apss_ipq5424_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static struct clk_regmap *apss_ipq5424_clks[] = {
+ [APSS_PLL_EARLY] = &ipq5424_apss_pll.clkr,
+ [APSS_SILVER_CLK_SRC] = &apss_silver_clk_src.clkr,
+ [APSS_SILVER_CORE_CLK] = &apss_silver_core_clk.clkr,
+ [L3_PLL] = &ipq5424_l3_pll.clkr,
+ [L3_CLK_SRC] = &l3_clk_src.clkr,
+ [L3_CORE_CLK] = &l3_core_clk.clkr,
+
+};
+
+#define IPQ_APPS_PLL_ID (5424 * 3) /* some unique value */
+
+static const struct qcom_icc_hws_data icc_ipq5424_cpu_l3[] = {
+ { MASTER_CPU, SLAVE_L3, L3_CORE_CLK },
+};
+
+static const struct qcom_cc_desc apss_ipq5424_desc = {
+ .config = &apss_ipq5424_regmap_config,
+ .clks = apss_ipq5424_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq5424_clks),
+ .icc_hws = icc_ipq5424_cpu_l3,
+ .num_icc_hws = ARRAY_SIZE(icc_ipq5424_cpu_l3),
+ .icc_first_node_id = IPQ_APPS_PLL_ID,
+};
+
+static const struct alpha_pll_config apss_pll_config = {
+ .l = 0x3b,
+ .config_ctl_val = 0x08200920,
+ .config_ctl_hi_val = 0x05008001,
+ .config_ctl_hi1_val = 0x04000000,
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x0,
+ .test_ctl_hi1_val = 0x0,
+ .user_ctl_val = 0x1,
+ .early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+};
+
+static const struct alpha_pll_config l3_pll_config = {
+ .l = 0x29,
+ .config_ctl_val = 0x08200920,
+ .config_ctl_hi_val = 0x05008001,
+ .config_ctl_hi1_val = 0x04000000,
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x0,
+ .test_ctl_hi1_val = 0x0,
+ .user_ctl_val = 0x1,
+ .early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+};
+
+static int apss_ipq5424_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, &apss_ipq5424_regmap_config);
+ if (!regmap)
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(&ipq5424_l3_pll, regmap, &l3_pll_config);
+
+ clk_alpha_pll_configure(&ipq5424_apss_pll, regmap, &apss_pll_config);
+
+ ret = qcom_cc_really_probe(dev, &apss_ipq5424_desc, regmap);
+ if (!ret)
+ dev_dbg(&pdev->dev, "Registered APSS & L3 clock provider\n");
+
+ return ret;
+}
+
+static const struct of_device_id apss_ipq5424_match_table[] = {
+ { .compatible = "qcom,ipq5424-apss-clk" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, apss_ipq5424_match_table);
+
+static struct platform_driver apss_ipq5424_driver = {
+ .probe = apss_ipq5424_probe,
+ .driver = {
+ .name = "apss-ipq5424-clk",
+ .of_match_table = apss_ipq5424_match_table,
+ },
+};
+
+module_platform_driver(apss_ipq5424_driver);
+
+MODULE_DESCRIPTION("QCOM APSS IPQ5424 CLK Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424
2025-07-23 11:08 [PATCH 0/4] Enable cpufreq for IPQ5424 Varadarajan Narayanan
2025-07-23 11:08 ` [PATCH v2 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller Varadarajan Narayanan
2025-07-23 11:08 ` [PATCH v2 2/4] clk: qcom: apss-ipq5424: " Varadarajan Narayanan
@ 2025-07-23 11:08 ` Varadarajan Narayanan
2025-07-23 11:08 ` [PATCH v2 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq Varadarajan Narayanan
3 siblings, 0 replies; 9+ messages in thread
From: Varadarajan Narayanan @ 2025-07-23 11:08 UTC (permalink / raw)
To: andersson, mturquette, sboyd, robh, krzk+dt, conor+dt,
konradybcio, rafael, viresh.kumar, ilia.lin, djakov,
quic_srichara, quic_mdalam, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-pm
Cc: Konrad Dybcio, Varadarajan Narayanan
From: Md Sadre Alam <quic_mdalam@quicinc.com>
IPQ5424 have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.
Added support for ipq5424 on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.
nvmem driver also creates the "cpufreq-dt" platform_device after
passing the version matching data to the OPP framework so that the
cpufreq-dt handles the actual cpufreq implementation.
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
[ Changed '!=' based check to '==' based check ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Add Reviewed-by: Konrad
Change speed bin check to == instead of !=
--
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 015dd393eaba..de1769649368 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -191,6 +191,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "ti,am62p5", },
{ .compatible = "qcom,ipq5332", },
+ { .compatible = "qcom,ipq5424", },
{ .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,ipq8074", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 54f8117103c8..765a5bb81829 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -200,6 +200,10 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
case QCOM_ID_IPQ9574:
drv->versions = 1 << (unsigned int)(*speedbin);
break;
+ case QCOM_ID_IPQ5424:
+ case QCOM_ID_IPQ5404:
+ drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0);
+ break;
case QCOM_ID_MSM8996SG:
case QCOM_ID_APQ8096SG:
drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
@@ -591,6 +595,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_u
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq5332", .data = &match_data_kryo },
+ { .compatible = "qcom,ipq5424", .data = &match_data_kryo },
{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq
2025-07-23 11:08 [PATCH 0/4] Enable cpufreq for IPQ5424 Varadarajan Narayanan
` (2 preceding siblings ...)
2025-07-23 11:08 ` [PATCH v2 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424 Varadarajan Narayanan
@ 2025-07-23 11:08 ` Varadarajan Narayanan
2025-07-23 13:33 ` Konrad Dybcio
3 siblings, 1 reply; 9+ messages in thread
From: Varadarajan Narayanan @ 2025-07-23 11:08 UTC (permalink / raw)
To: andersson, mturquette, sboyd, robh, krzk+dt, conor+dt,
konradybcio, rafael, viresh.kumar, ilia.lin, djakov,
quic_srichara, quic_mdalam, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-pm
Cc: Varadarajan Narayanan
From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for
CPU clock scaling.
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related entries, fix dt-bindings errors ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Add 'interconnects' to cpu nodes
Add 'opp-peak-kBps' to opp table
Add '#interconnect-cells' to apss_clk
Remove unnecessary comment
Fix dt-binding-errors in qfprom node
---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 65 +++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 2eea8a078595..39d394f49789 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
@@ -52,6 +53,12 @@ cpu0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;
+ interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
+
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -72,6 +79,11 @@ cpu1: cpu@100 {
enable-method = "psci";
reg = <0x100>;
next-level-cache = <&l2_100>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;
+ interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_100: l2-cache {
compatible = "cache";
@@ -87,6 +99,11 @@ cpu2: cpu@200 {
enable-method = "psci";
reg = <0x200>;
next-level-cache = <&l2_200>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;
+ interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_200: l2-cache {
compatible = "cache";
@@ -102,6 +119,11 @@ cpu3: cpu@300 {
enable-method = "psci";
reg = <0x300>;
next-level-cache = <&l2_300>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;
+ interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_300: l2-cache {
compatible = "cache";
@@ -119,6 +141,28 @@ scm {
};
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1>;
+ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ opp-peak-kBps = <984000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <2>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ opp-peak-kBps = <1272000>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -388,6 +432,18 @@ system-cache-controller@800000 {
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
};
+ qfprom@a6000 {
+ compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
+ reg = <0x0 0x000a6000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@234 {
+ reg = <0x234 0x1>;
+ bits = <0 8>;
+ };
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5424-tlmm";
reg = <0 0x01000000 0 0x300000>;
@@ -730,6 +786,15 @@ frame@f42d000 {
};
};
+ apss_clk: apss-clock@fa80000 {
+ compatible = "qcom,ipq5424-apss-clk";
+ reg = <0x0 0x0fa80000 0x0 0x20000>;
+ clocks = <&xo_board>, <&gcc GPLL0>;
+ clock-names = "xo", "gpll0";
+ #clock-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
pcie3: pcie@40000000 {
compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
reg = <0x0 0x40000000 0x0 0xf1c>,
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread