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Thu, 31 Jul 2025 22:31:21 -0700 (PDT) Date: Fri, 1 Aug 2025 08:31:20 +0300 From: Abel Vesa To: Taniya Das Cc: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur Message-ID: References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> <784545d0-2173-4a8b-9d5d-bee11226351e@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <784545d0-2173-4a8b-9d5d-bee11226351e@oss.qualcomm.com> On 25-08-01 10:02:15, Taniya Das wrote: > > > On 7/30/2025 4:55 PM, Abel Vesa wrote: > > On 25-07-29 11:12:37, Taniya Das wrote: > >> Add a clock driver for the TCSR clock controller found on Glymur, which > >> provides refclks for PCIE, USB, and UFS. > >> > >> Signed-off-by: Taniya Das > >> --- > >> drivers/clk/qcom/Kconfig | 8 ++ > >> drivers/clk/qcom/Makefile | 1 + > >> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ > >> 3 files changed, 266 insertions(+) > >> > > > > [...] > > > >> + > >> +static struct clk_branch tcsr_edp_clkref_en = { > >> + .halt_reg = 0x1c, > >> + .halt_check = BRANCH_HALT_DELAY, > >> + .clkr = { > >> + .enable_reg = 0x1c, > >> + .enable_mask = BIT(0), > >> + .hw.init = &(const struct clk_init_data) { > >> + .name = "tcsr_edp_clkref_en", > >> + .ops = &clk_branch2_ops, > > > > As discussed off-list, these clocks need to have the bi_tcxo as parent. > > > > Otherwise, as far as the CCF is concerned these clocks will have rate 0, > > which is obviously not the case. > > > > Bringing this here since there is a disconnect between X Elite and > > Glymur w.r.t this now. > > > The ref clocks are not required to be have a parent of bi_tcxo as these > ideally can be left enabled(as a subsystem requirement) even if HLOS > (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from > HLOS/APSS will not allow APSS to collapse. Is there a scenario where the APSS is collapsed and still the ref clock needs to stay enabled ? Sorry, this doesn't make sense to me. > > If any consumers needs the clock rate, the driver should take the > BI_TCXO handle. This kind of breaks the CCF design. If the ref clock is a gate of the bi_tcxo HW-wise, then not marking it so in CCF is wrong. Passing the bi_tcxo to the PHYs separately because of this, makes the assumption that the PHY drivers should know not to disable the bi_tcxo themselves either. > > > -- > Thanks, > Taniya Das >