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From: Niklas Cassel <cassel@kernel.org>
To: luyulin@eswincomputing.com
Cc: hehuan1@eswincomputing.com, dlemoal@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	linux-ide@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, p.zabel@pengutronix.de,
	ningyu@eswincomputing.com, linmin@eswincomputing.com,
	Serge Semin <fancer.lancer@gmail.com>
Subject: Re: Re: [PATCH v1 1/2] dt-bindings: sata: eswin: Document for EIC7700 SoC
Date: Thu, 14 Aug 2025 16:32:40 +0200	[thread overview]
Message-ID: <aJ3ziEwmGF-KLPuT@ryzen> (raw)
In-Reply-To: <2630d08e.133.198a7fe5583.Coremail.luyulin@eswincomputing.com>

Hello Yulin,

On Thu, Aug 14, 2025 at 05:51:59PM +0800, luyulin@eswincomputing.com wrote:
> Thank you very much for your constructive suggestions. Based on your advice,
> I have optimized both the driver and the YAML program.
> I sincerely apologize for the delayed response to your suggestions.

No need to apologize for anything :)


> > The good news is that snps,dwc-ahci-common.yaml has defined and documented
> > all the SATA clocks and resets for your board already (a lot of them which
> > you missed to include in this binding).
> > 
> > 
> > Looking quickly at:
> > eswin,hsp_sp_csr = <&hsp_sp_csr 0x1050>;
> > 
> > I can't help to wonder if these regs shouldn't be in a SATA PHY binding
> > instead.
> > 
> > Do e.g. a
> > $ git grep -A 20 snps,dwc-ahci arch/
> > 
> > There are multiple examples that use a PHY driver.
> > 
> > If you were to implement a PHY driver, it is possible that you would
> > not need to create a new (AHCI) DT binding at all, you could probably
> > just add your compatible string to snps,dwc-ahci.yaml, as (from a quick)
> > glance, all the only platform specific things appear to be PHY related.
> > 
> Thank you very much for your expert advice. I have already implemented a 
> independent PHY driver, while the controller driver utilizes ahci_dwc.c.
> Due to our hardware platform's SATA controller has specific constraints on clock, reset
> and port resources, I think adding these to snps,dwc-ahci.yaml might compromise its readability.
> Following reference implementations from other vendors in the Linux kernel, 
> such as rockchip,dwc-ahci.yaml, amlogic,axg-pcie.yaml and others, I plan to create 
> a new eswin,eic7700-ahci.yaml to describe these specifications.
> Based on your professional experience, would you consider this approach acceptable?

That sounds like a good approach.

When you create your device tree binding, make sure to reference
snps,dwc-ahci-common.yaml, like the other DWC based bindings:

$ git grep snps,dwc-ahci-common.yaml
baikal,bt1-ahci.yaml:  - $ref: snps,dwc-ahci-common.yaml#
baikal,bt1-ahci.yaml:    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
rockchip,dwc-ahci.yaml:    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
rockchip,dwc-ahci.yaml:  - $ref: snps,dwc-ahci-common.yaml#
snps,dwc-ahci.yaml:  - $ref: snps,dwc-ahci-common.yaml#
snps,dwc-ahci.yaml:    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port


Kind regards,
Niklas

  reply	other threads:[~2025-08-14 14:32 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15  8:51 [PATCH v1 0/2] ESWIN EIC7700 sata driver hehuan1
2025-05-15  8:57 ` [PATCH v1 1/2] dt-bindings: sata: eswin: Document for EIC7700 SoC hehuan1
2025-05-15 10:18   ` Rob Herring (Arm)
2025-05-15 11:25   ` Niklas Cassel
2025-08-14  9:51     ` luyulin
2025-08-14 14:32       ` Niklas Cassel [this message]
2025-05-15  9:00 ` [PATCH v1 2/2] sata: eswin: Add eic7700 sata driver hehuan1
2025-05-15 11:56   ` Niklas Cassel
2025-05-16 14:33   ` kernel test robot

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