[PATCH 0/3] Adding device tree and binding for Nvidia mgx cx8 switchboard

[PATCH 0/3] Adding device tree and binding for Nvidia mgx cx8 switchboard

[Marc Olberding]

Patch 1 Adds the binding for the Nvidia mgx cx8 switchboard
Patch 2 Adds dtsi's for the mgx cx8 switchboard itself
Patch 3 Adds the dts for the mgx cx8 switchboard motherboard reference implementation.

This is an Aspeed AST2600 based reference implementation for a BMC
managing an Nvidia mgx cx8 switchboard. Dtsi files are broken out for
managing the mgx cx8 switchboard over i2c, so that others may reuse these
if they choose to implement their own board. There are two dtsi files
since the i2c topology is not symmetric between busses going to the mgx cx8
switchboard.

Reference to Ast2600 SoC [1].

Link: https://www.aspeedtech.com/server_ast2600/ [1]
 

Signed-off-by: Marc Olberding <molberding@nvidia.com>
---
Marc Olberding (3):
      dt-bindings: arm: aspeed: Add Nvidia's mgx4u BMC
      ARM: dts: aspeed: Add device tree includes for the cx8 switchboard
      ARM: dts: aspeed: Add device tree for mgx4u BMC

 .../devicetree/bindings/arm/aspeed/aspeed.yaml     |    1 +
 arch/arm/boot/dts/aspeed/Makefile                  |    1 +
 .../boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts    | 1078 ++++++++++++++++++++
 .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    |   80 ++
 .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    |   80 ++
 5 files changed, 1240 insertions(+)
---
base-commit: 7bac2c97af4078d7a627500c9bcdd5b033f97718
change-id: 20250813-mgx4u_devicetree-c2e130607089

Best regards,
-- 
Marc Olberding <molberding@nvidia.com>

[PATCH 1/3] dt-bindings: arm: aspeed: Add Nvidia's mgx4u BMC

[Marc Olberding]

Adds a compatible string for Nvidia's mgx4u BMC board.

Signed-off-by: Marc Olberding <molberding@nvidia.com>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index a3736f13413057ed45791bd0bf655030e90ce3e4..b7ee725c3bdbd99b6ac0c8d5184648bfe6740921 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -99,6 +99,7 @@ properties:
               - inventec,transformer-bmc
               - jabil,rbp-bmc
               - nvidia,gb200nvl-bmc
+              - nvidia,mgx4u
               - qcom,dc-scm-v1-bmc
               - quanta,s6q-bmc
               - ufispace,ncplite-bmc

-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: arm: aspeed: Add Nvidia's mgx4u BMC

[Krzysztof Kozlowski]

On 15/08/2025 21:45, Marc Olberding wrote:
> Adds a compatible string for Nvidia's mgx4u BMC board.
> 
> Signed-off-by: Marc Olberding <molberding@nvidia.com>
> ---
>  Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

[Marc Olberding]

The mgx cx8 switchboard is used to network mgx GPUs

Signed-off-by: Marc Olberding <molberding@nvidia.com>
---
 .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    | 80 ++++++++++++++++++++++
 .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    | 80 ++++++++++++++++++++++
 2 files changed, 160 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..051c8cf0b7d12b1fa4c84db896ca480b21627e23
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+eeprom@56 {
+	compatible = "atmel,24c128";
+	reg = <0x56>;
+};
+
+gpio@26 {
+	compatible = "nxp,pca9555";
+	reg = <0x26>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	gpio-line-names = "WP_QSPI_CX0", "RST_SEQ_CX0_L",
+			  "BOOT_COMPLT_CX0", "FNP_CX0_L",
+			  "WP_FRU_CX0", "OVT_SHUTDOWN_CX0",
+			  "", "",
+			  "", "",
+			  "TMP_WARNING_CX0", "USB_HUB1_RST_L",
+			  "I2C_SWITCH1_RESET", "MCU1_GPIO",
+			  "MCU1_RST_N", "MCU1_RECOVERY_N";
+
+};
+
+i2c-mux@72 {
+	compatible = "nxp,pca9546";
+	reg = <0x72>;
+	i2c-mux-idle-disconnect;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+	};
+	i2c@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+	};
+	i2c@2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <2>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+	i2c@3 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <3>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+};
+
diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..cc8e71f374e100ba7f977138a21ea27a83ca36ed
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 Nvidia
+
+eeprom@56 {
+	compatible = "atmel,24c128";
+	reg = <0x56>;
+};
+
+gpio@26 {
+	compatible = "nxp,pca9555";
+	reg = <0x26>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	gpio-line-names = "WP_QSPI_CX1", "RST_SEQ_CX1_L",
+			  "BOOT_CMPLT_CX1", "FNP_CX1_L",
+			  "WP_FRU_CX1", "OVT_SHUTDOWN_CX1",
+			  "TMP_WARNING_CX1", "USB_HUB2_RST_L",
+			  "I2C_SWITCH2_RESET", "",
+			  "", "",
+			  "", "",
+			  "", "";
+};
+
+i2c-mux@72 {
+	compatible = "nxp,pca9546";
+	reg = <0x72>;
+	i2c-mux-idle-disconnect;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+	};
+	i2c@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+	};
+	i2c@2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <2>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+	i2c@3 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <3>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+};
+

-- 
2.34.1

Re: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

[Krzysztof Kozlowski]

On 15/08/2025 21:45, Marc Olberding wrote:
> The mgx cx8 switchboard is used to network mgx GPUs
> 
> Signed-off-by: Marc Olberding <molberding@nvidia.com>
> ---
>  .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    | 80 ++++++++++++++++++++++
>  .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    | 80 ++++++++++++++++++++++
>  2 files changed, 160 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..051c8cf0b7d12b1fa4c84db896ca480b21627e23
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later

Odd license. Since when GPL-3.0 is okay?

> +
> +eeprom@56 {
> +	compatible = "atmel,24c128";
> +	reg = <0x56>;
> +};
> +

This is some completely misplaced DTSI style. Don't do this...

Best regards,
Krzysztof

Re: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

[Marc Olberding]

On Sat, Aug 16, 2025 at 10:16:06AM +0200, Krzysztof Kozlowski wrote:
> 
> 
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> 
> Odd license. Since when GPL-3.0 is okay?
>
Ack, missed this. Will fix. 
> > +
> > +eeprom@56 {
> > +     compatible = "atmel,24c128";
> > +     reg = <0x56>;
> > +};
> > +
> 
> This is some completely misplaced DTSI style. Don't do this...

Thanks for the feedback. I'm not sure which piece of this is wrong.
Is the issue with having the contents of an i2c bus in a dtsi file?
If so, would you prefer that we abandon the dtsi all together and
add the contents in the dts file that's currently including it? This is
a seperate board from the one that the dts file describes, and others
may use it when integrating with the mgx-cx8 board, so the thought was to break it out
as a separate file. The only interface we have to describe between the two boards
is i2c, so this structure seemed appropriate. If not, I'll gladly get rid of it.

If its something other than the file structure, please let me know.

Best regards,
Marc Olberding

Re: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

[Krzysztof Kozlowski]

On 19/08/2025 21:09, Marc Olberding wrote:
> On Sat, Aug 16, 2025 at 10:16:06AM +0200, Krzysztof Kozlowski wrote:
>>
>>
>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>
>> Odd license. Since when GPL-3.0 is okay?
>>
> Ack, missed this. Will fix. 
>>> +
>>> +eeprom@56 {
>>> +     compatible = "atmel,24c128";
>>> +     reg = <0x56>;
>>> +};
>>> +
>>
>> This is some completely misplaced DTSI style. Don't do this...
> 
> Thanks for the feedback. I'm not sure which piece of this is wrong.
> Is the issue with having the contents of an i2c bus in a dtsi file?
> If so, would you prefer that we abandon the dtsi all together and

I think this should be just included in each bus needing it. It's really
odd to see a DTSI with top-level I2C devices.

Best regards,
Krzysztof

[PATCH 3/3] ARM: dts: aspeed: Add device tree for mgx4u BMC

[Marc Olberding]

The mgx4u is a BMC for a granite rapids based motherboard
that connects to a cx8 switchboard.

Signed-off-by: Marc Olberding <molberding@nvidia.com>
---
 arch/arm/boot/dts/aspeed/Makefile                  |    1 +
 .../boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts    | 1078 ++++++++++++++++++++
 2 files changed, 1079 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
index b3170fdd30969b5b064c5333aea136d3abfcbe72..f150ed0f2e48edb804b0588ef098edb3282b6292 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-lenovo-hr855xg2.dtb \
 	aspeed-bmc-microsoft-olympus.dtb \
 	aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
+	aspeed-bmc-nvidia-mgx4u.dtb \
 	aspeed-bmc-opp-lanyang.dtb \
 	aspeed-bmc-opp-mowgli.dtb \
 	aspeed-bmc-opp-nicole.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts
new file mode 100644
index 0000000000000000000000000000000000000000..beaf68d5b4bd73ec219a0d2d400f93cf05b0d34f
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts
@@ -0,0 +1,1078 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+	model = "MGX4U";
+	compatible = "nvidia,mgx4u", "aspeed,ast2600";
+
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+
+		i2c16 = &i2c5_mux_0;
+		i2c17 = &i2c5_mux_1;
+		i2c18 = &i2c5_mux_2;
+		i2c19 = &i2c5_mux_3;
+		i2c20 = &i2c5_mux_4;
+		i2c21 = &i2c5_mux_5;
+		i2c22 = &i2c5_mux_6;
+		i2c23 = &i2c5_mux_7;
+
+		i2c24 = &i2c6_mux_0;
+		i2c25 = &i2c6_mux_1;
+		i2c26 = &i2c6_mux_2;
+		i2c27 = &i2c6_mux_3;
+		i2c28 = &i2c6_mux_4;
+		i2c29 = &i2c6_mux_5;
+		i2c30 = &i2c6_mux_6;
+		i2c31 = &i2c6_mux_7;
+
+		i2c32 = &i2c7_1_mux_0;
+		i2c33 = &i2c7_1_mux_1;
+		i2c35 = &i2c7_1_mux_2;
+		i2c36 = &i2c7_1_mux_3;
+		i2c37 = &i2c7_mux_0;
+		i2c38 = &i2c7_mux_1;
+		i2c39 = &i2c7_mux_2;
+		i2c40 = &i2c7_mux_3;
+		i2c41 = &i2c7_mux_4;
+		i2c42 = &i2c7_mux_5;
+		i2c43 = &i2c7_mux_6;
+		i2c44 = &i2c7_mux_7;
+
+		i2c45 = &i2c0_mux_0;
+		i2c46 = &i2c0_mux_1;
+		i2c47 = &i2c0_mux_2;
+		i2c48 = &i2c0_mux_3;
+		i2c49 = &i2c0_mux_4;
+		i2c50 = &i2c0_mux_5;
+		i2c51 = &i2c0_mux_6;
+		i2c52 = &i2c0_mux_7;
+
+		i2c53 = &i2c0_1_mux_0;
+		i2c54 = &i2c0_1_mux_1;
+		i2c55 = &i2c0_1_mux_2;
+		i2c56 = &i2c0_1_mux_3;
+		i2c57 = &i2c0_1_mux_4;
+		i2c58 = &i2c0_1_mux_5;
+		i2c59 = &i2c0_1_mux_6;
+		i2c60 = &i2c0_1_mux_7;
+
+		i2c61 = &i2c3_mux_6;
+		i2c62 = &i2c3_mux_7;
+
+		i2c63 = &i2c9_mux_0;
+		i2c64 = &i2c9_mux_1;
+		i2c65 = &i2c9_mux_2;
+		i2c66 = &i2c9_mux_3;
+		i2c67 = &i2c9_mux_4;
+		i2c68 = &i2c9_mux_5;
+		i2c69 = &i2c9_mux_6;
+		i2c70 = &i2c9_mux_7;
+	};
+
+	chosen {
+		bootargs = "console=ttyS4,115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gfx_memory: framebuffer {
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+
+		video_engine_memory: jpegbuffer {
+			size = <0x02000000>;	/* 32M */
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emmc_controller {
+	status = "okay";
+};
+
+&emmc {
+	non-removable;
+	bus-width = <4>;
+	max-frequency = <100000000>;
+	clk-phase-mmc-hs200 = <9>, <225>;
+};
+
+&fmc {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+	};
+};
+
+&gfx {
+	memory-region = <&gfx_memory>;
+	status = "okay";
+};
+
+&gpio0 {
+	gpio-line-names =
+	/*A0-A7*/ "","","","","","","","",
+	/*B0-B7*/ "","","","","","","","RST_BMC_8211F_N",
+	/*C0-C7*/ "","","","","","","","",
+	/*D0-D7*/ "","","","","","","","",
+	/*E0-E7*/ "","","","","","","","",
+	/*F0-F7*/ "","RST_BIOSROM_1_BMC_N","","RST_SPI_PFRM1_R_N","","","SPI_BIOS_MUX_SEL","",
+	/*G0-G7*/ "","","","","","","","",
+	/*H0-H7*/ "","","","","","","","",
+	/*I0-I7*/ "","","","","","","","",
+	/*J0-J7*/ "","","","","","","","",
+	/*K0-K7*/ "","","","","","","","",
+	/*L0-L7*/ "","","","","","","","",
+	/*M0-M7*/ "","","","","","","","",
+	/*N0-N7*/ "","","","","","","","",
+	/*O0-O7*/ "","","","","","","","",
+	/*P0-P7*/ "","","","","","","","",
+	/*Q0-Q7*/ "","","","","","","","",
+	/*R0-R7*/ "","","","","","","","",
+	/*S0-S7*/ "","","","","","","","",
+	/*T0-T7*/ "","","","","","","","",
+	/*U0-U7*/ "","","","","","","","",
+	/*V0-V7*/ "","","SCM_HPM_STBY_RST_N","","SCM_HPM_STBY_EN","","","",
+	/*W0-W7*/ "","","","","","","","",
+	/*X0-X7*/ "","","","","","","","",
+	/*Y0-Y7*/ "","","","","","","","",
+	/*Z0-Z7*/ "","","","","","","","";
+	status = "okay";
+};
+
+&gpio1 {
+	gpio-line-names =
+	/*18A0-18A7*/ "","","","","","","","",
+	/*18B0-18B7*/ "","","","","SW_MAIN_EN","HOST_GLOBAL_WP_N","","",
+	/*18C0-18C7*/ "","","","","","","","",
+	/*18D0-18D7*/ "","","","","","","","",
+	/*18E0-18E3*/ "","","","";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	i2c-mux@73 {
+		compatible = "nxp,pca9548";
+		reg = <0x73>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c0_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_mux_1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c0_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom@51 {
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+		};
+
+		i2c0_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tmp75@4c {
+				compatible = "ti,tmp75";
+				reg = <0x4c>;
+			};
+		};
+
+		i2c0_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9548";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c0_1_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0_1_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c3 {
+	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9548";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c3_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9548";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c5_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	i2c-mux@70 {
+		reg = <0x70>;
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c6_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tmp75@4a {
+				compatible = "ti,tmp75";
+				reg = <0x4a>;
+			};
+
+			tmp75@4b {
+				compatible = "ti,tmp75";
+				reg = <0x4b>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c64";
+				reg = <0x51>;
+				pagesize = <32>;
+			};
+		};
+
+		i2c6_mux_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/*fan controller 0*/
+			max31790@20 {
+				compatible = "maxim,max31790";
+				reg = <0x20>;
+			};
+
+			/*fan controller 1*/
+			max31790@21 {
+				compatible = "maxim,max31790";
+				reg = <0x21>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c64";
+				reg = <0x57>;
+				pagesize = <32>;
+			};
+
+			hpmfanio: pca9555@27 {
+				compatible = "nxp,pca9555";
+				reg = <0x27>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&gpio0>;
+				interrupts = <11 0>;
+				gpio-line-names =
+						"HPM_FAN1_INSTALL", "HPM_FAN2_INSTALL",
+						"HPM_FAN3_INSTALL", "HPM_FAN4_INSTALL",
+						"HPM_FAN5_INSTALL", "",
+						"","";
+			};
+		 };
+
+		 i2c6_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		 };
+
+		 i2c6_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* 4056 fan board_EEPROM*/
+			eeprom@57 {
+				compatible = "atmel,24c64";
+				reg = <0x57>;
+				pagesize = <32>;
+			};
+
+			/*fan controller 0*/
+			max31790@20 {
+				compatible = "maxim,max31790";
+				reg = <0x20>;
+			};
+			/*fan controller 1*/
+			max31790@21 {
+				compatible = "maxim,max31790";
+				reg = <0x21>;
+			};
+
+			gpufanio: pca9555@27 {
+				compatible = "nxp,pca9555";
+				reg = <0x27>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&gpio0>;
+				interrupts = <11 0>;
+				gpio-line-names =
+						"GPU_FAN1_INSTALL", "GPU_FAN2_INSTALL",
+						"GPU_FAN3_INSTALL", "GPU_FAN4_INSTALL",
+						"GPU_FAN5_INSTALL", "",
+						"","";
+			};
+		 };
+
+		i2c6_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* IO board EEPROM*/
+			eeprom@57 {
+				compatible = "atmel,24c64";
+				reg = <0x57>;
+				pagesize = <32>;
+			};
+		};
+
+		i2c6_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c6_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c6_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c7 {
+	multi-master;
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c7_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c7_mux_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2c-mux@71 {
+				compatible = "nxp,pca9545";
+				reg = <0x71>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				i2c7_1_mux_0: i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+
+				i2c7_1_mux_1: i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					eeprom@55 {
+						compatible = "atmel,24c64";
+						reg = <0x55>;
+						pagesize = <32>;
+					};
+
+					eeprom@50 {
+						compatible = "atmel,24c02";
+						reg = <0x50>;
+						pagesize = <32>;
+					};
+
+					eeprom@53 {
+						compatible = "atmel,24c02";
+						reg = <0x53>;
+						pagesize = <32>;
+					};
+				};
+
+				i2c7_1_mux_2: i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+
+				i2c7_1_mux_3: i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		i2c7_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c7_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* XDPE19284B - CPU0 PVCCIN VR */
+			xdpe152c4@60 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x60>;
+			};
+
+			/* XDPE19284B - CPU0 PVCCFA EHV FIVRA / PVCCINF_VR*/
+			xdpe152c4@62 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x62>;
+			};
+
+			/* XDPE19284B - CPU0 PVCCA EHV PVCCIN VR */
+			xdpe152c4@74 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x74>;
+			};
+
+			/* XDPE19284B - CPU0 PVVCCD0 & D1 VR */
+			xdpe152c4@76 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x76>;
+			};
+		};
+
+		i2c7_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* XDPE19284B - CPU1 PVCCIN VR */
+			xdpe152c4@60 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x60>;
+			};
+
+			/* XDPE19284B - CPU1 PVCCFA EHV FIVRA / PVCCINF_VR*/
+			xdpe152c4@62 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x62>;
+			};
+
+			/* XDPE19284B - CPU1 PVCCA EHV PVCCIN VR */
+			xdpe152c4@74 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x74>;
+			};
+
+			/* XDPE19284B - CPU1 PVVCCD0 & D1 VR */
+			xdpe152c4@76 {
+				compatible = "infineon,xdpe152c4";
+				reg = <0x76>;
+			};
+		};
+
+		i2c7_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c7_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c7_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c9_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-north.dtsi"
+		};
+
+		i2c9_mux_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-south.dtsi"
+		};
+
+		i2c9_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-north.dtsi"
+		};
+
+		i2c9_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-south.dtsi"
+		};
+
+		i2c9_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-north.dtsi"
+		};
+
+		i2c9_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-south.dtsi"
+		};
+
+		i2c9_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-north.dtsi"
+		};
+
+		i2c9_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+#include "nvidia-mgx-cx8-switch-south.dtsi"
+		};
+	};
+};
+
+&i2c10 {
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c10_mux_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_2: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_3: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_4: i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_5: i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_6: i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c10_mux_7: i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c12 {
+	status = "okay";
+
+	rtc@6f {
+		compatible = "nuvoton,nct3018y";
+		reg = <0x6f>;
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+	};
+};
+
+&mdio3 {
+	status = "okay";
+
+	ethphy3: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&mac2 {
+	pinctrl-names = "default";
+	phy-mode = "rmii";
+	pinctrl-0 = <&pinctrl_rmii3_default>;
+	use-ncsi;
+	status = "okay";
+};
+
+&mac3 {
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii4_default>;
+	status = "okay";
+};
+
+&peci0 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sdc {
+	status = "okay";
+};
+
+&sgpiom0 {
+	ngpios = <128>;
+	gpio-line-names =
+		"","LED_PORT80_0_N",
+		"","LED_PORT80_1_N",
+		"","LED_PORT80_2_N",
+		"","LED_PORT80_3_N",
+		"","LED_PORT80_4_N",
+		"","LED_PORT80_5_N",
+		"","LED_PORT80_6_N",
+		"","LED_PORT80_7_N",
+		"","CPLD_JTAG_OE_R_N",
+		"","RST_PE_SLOT_I2C_MUX_N",
+		"","ASSERT_CPU0_PROCHOT_N",
+		"","ASSERT_CPU1_PROCHOT_N",
+		"","BMC_CPU0_NMI_OUT_N",
+		"","BMC_CPU1_NMI_OUT_N",
+		"","CPLD_PWRBRK_N",
+		"","SPD_SWITCH_CTRL_N",
+		"","COM_DBG_MODE",
+		"","RST_CPU0_RTCRST_PLD","",
+		"EN_MON_VBAT","","BMC_RST_BTN_OUT",
+		"","BMC_PWR_BTN_OUT",
+		"","BMC_WAKE",
+		"","CPU_FRBK_OUT",
+		"","CPU0_BMC_INIT",
+		"","CPU1_BMC_INIT",
+		"","NCSI_BMC_CLK_EN",
+		"","NCSI_OCP_CLK_EN",
+		"","IRQ_CPU0_TPM",
+		"","UART_HPM_MUX",
+		"","DEBUG_BIT_0","","DEBUG_BIT_1",
+		"","DEBUG_BIT_2",
+		"FAN_4056_BOARD_ID_0","DEBUG_BIT_3",
+		"FAN_4056_BOARD_ID_1","DEBUG_BIT_4",
+		"FAN_4056_BOARD_ID_2","DEBUG_BIT_5",
+		"FAN_4056_BOARD_ID_3","DEBUG_BIT_6",
+		"FAN_8080_BOARD_ID_0","DEBUG_BIT_7",
+		"FAN_8080_BOARD_ID_1","LED_BMC_HBLED_CPLD_N",
+		"FAN_8080_BOARD_ID_2","LED_SYS_ALERT_CPLD",
+		"FAN_8080_BOARD_ID_3","LED_PWR_YEL_CPLD",
+		"FAN1_FRONT_TOP_INSTALL","",
+		"FAN2_FRONT_TOP_INSTALL","",
+		"FAN3_FRONT_TOP_INSTALL","",
+		"FAN4_FRONT_TOP_INSTALL","",
+		"FAN5_FRONT_TOP_INSTALL","",
+		"","",
+		"","",
+		"","",
+		"FAN9_REAR_INSTALL","",
+		"FAN_FRONT_SW0_FAIL","",
+		"FAN_REAR_SW0_FAIL","",
+		"FAN1_FRONT_BOT_INSTALL","",
+		"FAN2_FRONT_BOT_INSTALL","LED_UID_N",
+		"FAN3_FRONT_BOT_INSTALL","",
+		"FAN4_FRONT_BOT_INSTALL","",
+		"FAN5_FRONT_BOT_INSTALL","SPI_MUX3_EN",
+		"FAN1_REAR_INSTALL","SPI_MUX2_EN",
+		"FAN2_REAR_INSTALL","SPI_MUX1_EN",
+		"FAN3_REAR_INSTALL","SPI_MUX3_SEL",
+		"FAN4_REAR_INSTALL","SPI_MUX2_SEL",
+		"FAN5_REAR_INSTALL","SPI_MUX1_SEL",
+		"FAN6_REAR_INSTALL","PDB_RST",
+		"FAN7_REAR_INSTALL","PRE_STANDBY_DROP",
+		"FAN8_REAR_INSTALL","",
+		"MLB_BRD_SKU_ID0","",
+		"MLB_BRD_SKU_ID1","",
+		"MLB_BRD_SKU_ID2","",
+		"MLB_BRD_SKU_ID3","",
+		"MLB_BRD_REV_ID0","",
+		"MLB_BRD_REV_ID1","",
+		"M2_1_PRESENT","",
+		"M2_2_PRESENT","",
+		"M2_1_ALERT","",
+		"PASSWORD_CLEAR","",
+		"IRQ_PSYS_CRIT","",
+		"LEAKAGE_MONITOR_ALERT","",
+		"M2_2_ALERT","",
+		"RST_BTN","",
+		"PWR_BTN","",
+		"","",
+		"CPU1_MEM_VRHOT","",
+		"CPU0_MEM_VRHOT","",
+		"CPU1_VRHOT","",
+		"CPU0_VRHOT","",
+		"RST_PLTRST_MONITOR","",
+		"CPU_SLP_S3","",
+		"TPM_PRSNT","",
+		"HPM_HMC_PCIE_PERST","",
+		"CPU1_THERMTRIP","",
+		"CPU0_THERMTRIP","",
+		"CPU1_PROCHOT_CPLD","",
+		"CPU0_PROCHOT_CPLD","",
+		"CPU1_MEMTRIP","",
+		"CPU0_MEMTRIP","",
+		"CPU0_MEMHOT","",
+		"CPU1_MEMHOT","",
+		"CPU_ERR2","",
+		"CPU_ERR1","",
+		"CPU_ERR0","",
+		"CPU_CATERR","",
+		"CPU_RMCA","",
+		"","",
+		"CPU1_MON_FAIL","",
+		"CPU0_MON_FAIL","",
+		"PUS4_PRSNT_N","",
+		"PUS5_PRSNT_N","",
+		"PUS6_PRSNT_N","",
+		"PUS7_PRSNT_N","",
+		"PUS8_PRSNT_N","",
+		"PUS9_PRSNT_N","",
+		"PUS10_PRSNT_N","",
+		"PUS11_PRSNT_N","",
+		"PWRGD_CPU1_S0_PWROK","",
+		"PWRGD_CPU0_S0_PWROK","",
+		"","",
+		"PSU_SMBUS_ALERT_N","",
+		"PSU0_PRSNT_N","",
+		"PSU1_PRSNT_N","",
+		"PUS2_PRSNT_N","",
+		"PUS3_PRSNT_N","",
+		"CPU0_PRSNT_N","",
+		"CPU1_PRSNT_N","",
+		"CPU0_PWR_GOOD","",
+		"CPU1_PWR_GOOD","",
+		"PGD_SYS_PWROK","",
+		"BIOS_POST_CMPLT_N","",
+		"CPU0_CD_INIT_ERROR","",
+		"CPU1_CD_INIT_ERROR","";
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default>;
+	fmc-spi-user-mode;
+	status = "okay";
+
+	flash@0 {
+		m25p,fast-read;
+		label = "bios";
+		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <2>;
+		status = "okay";
+	};
+};
+
+&syscon {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&uart_routing {
+	status = "okay";
+};
+
+&uhci {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	memory-region = <&video_engine_memory>;
+	status = "okay";
+};

-- 
2.34.1

Re: [PATCH 3/3] ARM: dts: aspeed: Add device tree for mgx4u BMC

[Andrew Lunn]

> +&mac3 {
> +	phy-mode = "rgmii";

Does the PCB have extra long clock lines to impose the 2ns delay?

	Andrew

Re: [PATCH 3/3] ARM: dts: aspeed: Add device tree for mgx4u BMC

[Krzysztof Kozlowski]

On 15/08/2025 21:45, Marc Olberding wrote:
> +		i2c69 = &i2c9_mux_6;
> +		i2c70 = &i2c9_mux_7;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS4,115200n8";

No, use stdout.

> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x80000000>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		gfx_memory: framebuffer {
> +			size = <0x01000000>;
> +			alignment = <0x01000000>;
> +			compatible = "shared-dma-pool";
> +			reusable;
> +		};
> +
> +		video_engine_memory: jpegbuffer {
> +			size = <0x02000000>;	/* 32M */
> +			alignment = <0x01000000>;
> +			compatible = "shared-dma-pool";
> +			reusable;
> +		};
> +	};
> +};
> +
> +&ehci1 {
> +	status = "okay";
> +};
> +
> +&emmc_controller {
> +	status = "okay";
> +};
> +
> +&emmc {
> +	non-removable;
> +	bus-width = <4>;
> +	max-frequency = <100000000>;
> +	clk-phase-mmc-hs200 = <9>, <225>;
> +};
> +
> +&fmc {
> +	status = "okay";
> +
> +	flash@0 {
> +		status = "okay";
> +		m25p,fast-read;
> +		label = "bmc";
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;
> +		spi-max-frequency = <50000000>;
> +#include "openbmc-flash-layout-128.dtsi"
> +	};
> +};
> +
> +&gfx {
> +	memory-region = <&gfx_memory>;
> +	status = "okay";
> +};
> +
> +&gpio0 {
> +	gpio-line-names =
> +	/*A0-A7*/ "","","","","","","","",
> +	/*B0-B7*/ "","","","","","","","RST_BMC_8211F_N",
> +	/*C0-C7*/ "","","","","","","","",
> +	/*D0-D7*/ "","","","","","","","",
> +	/*E0-E7*/ "","","","","","","","",
> +	/*F0-F7*/ "","RST_BIOSROM_1_BMC_N","","RST_SPI_PFRM1_R_N","","","SPI_BIOS_MUX_SEL","",
> +	/*G0-G7*/ "","","","","","","","",
> +	/*H0-H7*/ "","","","","","","","",
> +	/*I0-I7*/ "","","","","","","","",
> +	/*J0-J7*/ "","","","","","","","",
> +	/*K0-K7*/ "","","","","","","","",
> +	/*L0-L7*/ "","","","","","","","",
> +	/*M0-M7*/ "","","","","","","","",
> +	/*N0-N7*/ "","","","","","","","",
> +	/*O0-O7*/ "","","","","","","","",
> +	/*P0-P7*/ "","","","","","","","",
> +	/*Q0-Q7*/ "","","","","","","","",
> +	/*R0-R7*/ "","","","","","","","",
> +	/*S0-S7*/ "","","","","","","","",
> +	/*T0-T7*/ "","","","","","","","",
> +	/*U0-U7*/ "","","","","","","","",
> +	/*V0-V7*/ "","","SCM_HPM_STBY_RST_N","","SCM_HPM_STBY_EN","","","",
> +	/*W0-W7*/ "","","","","","","","",
> +	/*X0-X7*/ "","","","","","","","",
> +	/*Y0-Y7*/ "","","","","","","","",
> +	/*Z0-Z7*/ "","","","","","","","";
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	gpio-line-names =
> +	/*18A0-18A7*/ "","","","","","","","",
> +	/*18B0-18B7*/ "","","","","SW_MAIN_EN","HOST_GLOBAL_WP_N","","",
> +	/*18C0-18C7*/ "","","","","","","","",
> +	/*18D0-18D7*/ "","","","","","","","",
> +	/*18E0-18E3*/ "","","","";
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	i2c-mux@73 {
> +		compatible = "nxp,pca9548";
> +		reg = <0x73>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c-mux-idle-disconnect;
> +
> +		i2c0_mux_0: i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_mux_1: i2c@1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +		};
> +
> +		i2c0_mux_2: i2c@2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_mux_3: i2c@3 {
> +			reg = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			eeprom@51 {
> +				compatible = "atmel,24c02";
> +				reg = <0x51>;
> +			};
> +		};
> +
> +		i2c0_mux_4: i2c@4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_mux_5: i2c@5 {
> +			reg = <5>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_mux_6: i2c@6 {
> +			reg = <6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			tmp75@4c {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> +				compatible = "ti,tmp75";
> +				reg = <0x4c>;
> +			};
> +		};
> +
> +		i2c0_mux_7: i2c@7 {
> +			reg = <7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	i2c-mux@77 {
> +		compatible = "nxp,pca9548";
> +		reg = <0x77>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c-mux-idle-disconnect;
> +
> +		i2c0_1_mux_0: i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_1: i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_2: i2c@2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_3: i2c@3 {
> +			reg = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_4: i2c@4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_5: i2c@5 {
> +			reg = <5>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_6: i2c@6 {
> +			reg = <6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c0_1_mux_7: i2c@7 {
> +			reg = <7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +};
> +
> +&i2c3 {
> +	status = "okay";
> +
> +	i2c-mux@72 {
> +		compatible = "nxp,pca9548";
> +		reg = <0x72>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c-mux-idle-disconnect;
> +
> +		i2c3_mux_6: i2c@6 {
> +			reg = <6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c3_mux_7: i2c@7 {
> +			reg = <7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +};
> +
> +&i2c4 {
> +	status = "okay";
> +};
> +
> +&i2c5 {
> +	status = "okay";
> +
> +	i2c-mux@77 {
> +		compatible = "nxp,pca9548";
> +		reg = <0x77>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c-mux-idle-disconnect;
> +
> +		i2c5_mux_0: i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_1: i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_2: i2c@2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_3: i2c@3 {
> +			reg = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_4: i2c@4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_5: i2c@5 {
> +			reg = <5>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_6: i2c@6 {
> +			reg = <6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c5_mux_7: i2c@7 {
> +			reg = <7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +};
> +
> +&i2c6 {
> +	status = "okay";
> +
> +	i2c-mux@70 {
> +		reg = <0x70>;
> +		compatible = "nxp,pca9548";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c-mux-idle-disconnect;
> +
> +		i2c6_mux_0: i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			tmp75@4a {
> +				compatible = "ti,tmp75";
> +				reg = <0x4a>;
> +			};
> +
> +			tmp75@4b {
> +				compatible = "ti,tmp75";
> +				reg = <0x4b>;
> +			};
> +
> +			eeprom@51 {
> +				compatible = "atmel,24c64";
> +				reg = <0x51>;
> +				pagesize = <32>;
> +			};
> +		};
> +
> +		i2c6_mux_1: i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/*fan controller 0*/
> +			max31790@20 {
> +				compatible = "maxim,max31790";
> +				reg = <0x20>;
> +			};
> +
> +			/*fan controller 1*/
> +			max31790@21 {
> +				compatible = "maxim,max31790";
> +				reg = <0x21>;
> +			};
> +
> +			eeprom@57 {
> +				compatible = "atmel,24c64";
> +				reg = <0x57>;
> +				pagesize = <32>;
> +			};
> +
> +			hpmfanio: pca9555@27 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +				compatible = "nxp,pca9555";
> +				reg = <0x27>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupt-parent = <&gpio0>;
> +				interrupts = <11 0>;
> +				gpio-line-names =
> +						"HPM_FAN1_INSTALL", "HPM_FAN2_INSTALL",
> +						"HPM_FAN3_INSTALL", "HPM_FAN4_INSTALL",
> +						"HPM_FAN5_INSTALL", "",
> +						"","";
> +			};
> +		 };
> +
> +		 i2c6_mux_2: i2c@2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		 };
> +
> +		 i2c6_mux_3: i2c@3 {
> +			reg = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* 4056 fan board_EEPROM*/
> +			eeprom@57 {
> +				compatible = "atmel,24c64";
> +				reg = <0x57>;
> +				pagesize = <32>;
> +			};
> +
> +			/*fan controller 0*/
> +			max31790@20 {
> +				compatible = "maxim,max31790";
> +				reg = <0x20>;
> +			};
> +			/*fan controller 1*/
> +			max31790@21 {
> +				compatible = "maxim,max31790";
> +				reg = <0x21>;
> +			};
> +
> +			gpufanio: pca9555@27 {
> +				compatible = "nxp,pca9555";
> +				reg = <0x27>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupt-parent = <&gpio0>;
> +				interrupts = <11 0>;
> +				gpio-line-names =
> +						"GPU_FAN1_INSTALL", "GPU_FAN2_INSTALL",
> +						"GPU_FAN3_INSTALL", "GPU_FAN4_INSTALL",
> +						"GPU_FAN5_INSTALL", "",
> +						"","";
> +			};
> +		 };
> +
> +		i2c6_mux_4: i2c@4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* IO board EEPROM*/
> +			eeprom@57 {
> +				compatible = "atmel,24c64";
> +				reg = <0x57>;
> +				pagesize = <32>;
> +			};
> +		};
> +
> +		i2c6_mux_5: i2c@5 {
> +			reg = <5>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c6_mux_6: i2c@6 {
> +			reg = <6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c6_mux_7: i2c@7 {
> +			reg = <7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +};
> +
> +&i2c7 {
> +	multi-master;
> +	status = "okay";
> +
> +	i2c-mux@70 {
> +		compatible = "nxp,pca9548";
> +		reg = <0x70>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		i2c7_mux_0: i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c7_mux_1: i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			i2c-mux@71 {
> +				compatible = "nxp,pca9545";
> +				reg = <0x71>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				i2c7_1_mux_0: i2c@0 {
> +					reg = <0>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +
> +				i2c7_1_mux_1: i2c@1 {
> +					reg = <1>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					eeprom@55 {
> +						compatible = "atmel,24c64";
> +						reg = <0x55>;
> +						pagesize = <32>;
> +					};
> +
> +					eeprom@50 {
> +						compatible = "atmel,24c02";
> +						reg = <0x50>;
> +						pagesize = <32>;
> +					};
> +
> +					eeprom@53 {
> +						compatible = "atmel,24c02";
> +						reg = <0x53>;
> +						pagesize = <32>;
> +					};
> +				};
> +
> +				i2c7_1_mux_2: i2c@2 {
> +					reg = <2>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +
> +				i2c7_1_mux_3: i2c@3 {
> +					reg = <3>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +			};
> +		};
> +
> +		i2c7_mux_2: i2c@2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c7_mux_3: i2c@3 {
> +			reg = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* XDPE19284B - CPU0 PVCCIN VR */
> +			xdpe152c4@60 {
> +				compatible = "infineon,xdpe152c4";
> +				reg = <0x60>;
> +			};
> +
> +			/* XDPE19284B - CPU0 PVCCFA EHV FIVRA / PVCCINF_VR*/
> +			xdpe152c4@62 {
> +				compatible = "infineon,xdpe152c4";
> +				reg = <0x62>;
> +			};
> +
> +			/* XDPE19284B - CPU0 PVCCA EHV PVCCIN VR */
> +			xdpe152c4@74 {
> +				compatible = "infineon,xdpe152c4";
> +				reg = <0x74>;
> +			};
> +
> +			/* XDPE19284B - CPU0 PVVCCD0 & D1 VR */
> +			xdpe152c4@76 {
> +				compatible = "infineon,xdpe152c4";
> +				reg = <0x76>;
> +			};
> +		};
> +
> +		i2c7_mux_4: i2c@4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* XDPE19284B - CPU1 PVCCIN VR */
> +			xdpe152c4@60 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation




Best regards,
Krzysztof

Re: [PATCH 0/3] Adding device tree and binding for Nvidia mgx cx8 switchboard

[Rob Herring (Arm)]

On Fri, 15 Aug 2025 12:45:54 -0700, Marc Olberding wrote:
> Patch 1 Adds the binding for the Nvidia mgx cx8 switchboard
> Patch 2 Adds dtsi's for the mgx cx8 switchboard itself
> Patch 3 Adds the dts for the mgx cx8 switchboard motherboard reference implementation.
> 
> This is an Aspeed AST2600 based reference implementation for a BMC
> managing an Nvidia mgx cx8 switchboard. Dtsi files are broken out for
> managing the mgx cx8 switchboard over i2c, so that others may reuse these
> if they choose to implement their own board. There are two dtsi files
> since the i2c topology is not symmetric between busses going to the mgx cx8
> switchboard.
> 
> Reference to Ast2600 SoC [1].
> 
> Link: https://www.aspeedtech.com/server_ast2600/ [1]
> 
> 
> Signed-off-by: Marc Olberding <molberding@nvidia.com>
> ---
> Marc Olberding (3):
>       dt-bindings: arm: aspeed: Add Nvidia's mgx4u BMC
>       ARM: dts: aspeed: Add device tree includes for the cx8 switchboard
>       ARM: dts: aspeed: Add device tree for mgx4u BMC
> 
>  .../devicetree/bindings/arm/aspeed/aspeed.yaml     |    1 +
>  arch/arm/boot/dts/aspeed/Makefile                  |    1 +
>  .../boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts    | 1078 ++++++++++++++++++++
>  .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    |   80 ++
>  .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    |   80 ++
>  5 files changed, 1240 insertions(+)
> ---
> base-commit: 7bac2c97af4078d7a627500c9bcdd5b033f97718
> change-id: 20250813-mgx4u_devicetree-c2e130607089
> 
> Best regards,
> --
> Marc Olberding <molberding@nvidia.com>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 7bac2c97af4078d7a627500c9bcdd5b033f97718

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/aspeed/' for 20250815-mgx4u_devicetree-v1-0-66db6fa5a7e4@nvidia.com:

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: timer (arm,armv7-timer): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /sdram@1e6e0000: failed to match any schema with compatible: ['aspeed,ast2600-sdram-edac', 'syscon']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: bus@1e600000 (aspeed,ast2600-ahbc): compatible: ['aspeed,ast2600-ahbc', 'syscon'] is too long
	from schema $id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: spi@1e630000 (aspeed,ast2600-spi): Unevaluated properties are not allowed ('fmc-spi-user-mode' was unexpected)
	from schema $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: syscon@1e6e2000 (aspeed,ast2600-scu): 'smp-memram@180' does not match any of the regexes: '^interrupt-controller@[0-9a-f]+$', '^p2a-control@[0-9a-f]+$', '^pinctrl(@[0-9a-f]+)?$', '^pinctrl-[0-9]+$', '^silicon-id@[0-9a-f]+$'
	from schema $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e6e0000/syscon@1e6e2000/smp-memram@180: failed to match any schema with compatible: ['aspeed,ast2600-smpmem']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e6e0000/display@1e6e6000: failed to match any schema with compatible: ['aspeed,ast2600-gfx', 'syscon']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: adc@1e6e9000 (aspeed,ast2600-adc0): 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: adc@1e6e9100 (aspeed,ast2600-adc1): 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: crypto@1e6fa000 (aspeed,ast2600-acry): 'aspeed,ahbc' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: sdc@1e740000 (aspeed,ast2600-sd-controller): sdhci@1e740100:compatible: ['aspeed,ast2600-sdhci', 'sdhci'] is too long
	from schema $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: sdc@1e740000 (aspeed,ast2600-sd-controller): sdhci@1e740200:compatible: ['aspeed,ast2600-sdhci', 'sdhci'] is too long
	from schema $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/sdc@1e740000/sdhci@1e740100: failed to match any schema with compatible: ['aspeed,ast2600-sdhci', 'sdhci']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/sdc@1e740000/sdhci@1e740200: failed to match any schema with compatible: ['aspeed,ast2600-sdhci', 'sdhci']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e780000/timer@1e782000: failed to match any schema with compatible: ['aspeed,ast2600-timer']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: lpc@1e789000 (aspeed,ast2600-lpc-v2): reg-io-width: 4 is not of type 'object'
	from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: lpc@1e789000 (aspeed,ast2600-lpc-v2): lpc-snoop@80: 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: kcs@24 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: kcs@28 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: kcs@2c (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: kcs@114 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e780000/lpc@1e789000/lhc@a0: failed to match any schema with compatible: ['aspeed,ast2600-lhc']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e780000/lpc@1e789000/ibt@140: failed to match any schema with compatible: ['aspeed,ast2600-ibt-bmc']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: fsi@1e79b000 (aspeed,ast2600-fsi-master): compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] is too long
	from schema $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e790000/fsi@1e79b000: failed to match any schema with compatible: ['aspeed,ast2600-fsi-master', 'fsi-master']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: fsi@1e79b100 (aspeed,ast2600-fsi-master): compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] is too long
	from schema $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e790000/fsi@1e79b100: failed to match any schema with compatible: ['aspeed,ast2600-fsi-master', 'fsi-master']
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dtb: /ahb/apb@1e790000/dma-controller@1e79e000: failed to match any schema with compatible: ['aspeed,ast2600-udma']

Re: [PATCH 0/3] Adding device tree and binding for Nvidia mgx cx8 switchboard

[Rob Herring]

On Fri, Aug 15, 2025 at 06:38:54PM -0500, Rob Herring (Arm) wrote:
> 
> On Fri, 15 Aug 2025 12:45:54 -0700, Marc Olberding wrote:
> > Patch 1 Adds the binding for the Nvidia mgx cx8 switchboard
> > Patch 2 Adds dtsi's for the mgx cx8 switchboard itself
> > Patch 3 Adds the dts for the mgx cx8 switchboard motherboard reference implementation.
> > 
> > This is an Aspeed AST2600 based reference implementation for a BMC
> > managing an Nvidia mgx cx8 switchboard. Dtsi files are broken out for
> > managing the mgx cx8 switchboard over i2c, so that others may reuse these
> > if they choose to implement their own board. There are two dtsi files
> > since the i2c topology is not symmetric between busses going to the mgx cx8
> > switchboard.
> > 
> > Reference to Ast2600 SoC [1].
> > 
> > Link: https://www.aspeedtech.com/server_ast2600/ [1]
> > 
> > 
> > Signed-off-by: Marc Olberding <molberding@nvidia.com>
> > ---
> > Marc Olberding (3):
> >       dt-bindings: arm: aspeed: Add Nvidia's mgx4u BMC
> >       ARM: dts: aspeed: Add device tree includes for the cx8 switchboard
> >       ARM: dts: aspeed: Add device tree for mgx4u BMC
> > 
> >  .../devicetree/bindings/arm/aspeed/aspeed.yaml     |    1 +
> >  arch/arm/boot/dts/aspeed/Makefile                  |    1 +
> >  .../boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts    | 1078 ++++++++++++++++++++
> >  .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    |   80 ++
> >  .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    |   80 ++
> >  5 files changed, 1240 insertions(+)
> > ---
> > base-commit: 7bac2c97af4078d7a627500c9bcdd5b033f97718

next-20250521!? Why are you using linux-next from 3 months ago?

Base your patches on the latest rc1 unless you have some dependency on 
post rc1 changes. Usually that means you need to base your tree on the 
maintainer's tree the series applies to (ASpeed in this case). 
The *current* linux-next is a shortcut for that.

Rob