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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70ba9097dc4sm109917596d6.26.2025.08.21.11.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 11:29:57 -0700 (PDT) Date: Thu, 21 Aug 2025 14:29:55 -0400 From: Brian Masney To: Icenowy Zheng Cc: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Michal Wilczynski , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] clk: thead: support changing DPU pixel clock rate Message-ID: References: <20250812054258.1968351-1-uwu@icenowy.me> <20250812054258.1968351-3-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250812054258.1968351-3-uwu@icenowy.me> User-Agent: Mutt/2.2.14 (2025-02-20) On Tue, Aug 12, 2025 at 01:42:56PM +0800, Icenowy Zheng wrote: > The DPU pixel clock rate corresponds to the required dot clock of the > display mode, so it needs to be tweakable. > > Add support to change it, by adding generic divider setting code, > arming the code to the dpu0/dpu1 clocks, and setting the pixel clock > connected to the DPU (after a gate) to CLK_SET_RATE_PARENT to propagate > it to the dividers. > > Signed-off-by: Icenowy Zheng > --- > drivers/clk/thead/clk-th1520-ap.c | 87 +++++++++++++++++++++++++++++-- > 1 file changed, 82 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c > index 2f87c7c2c3baf..3e81f3051cd6c 100644 > --- a/drivers/clk/thead/clk-th1520-ap.c > +++ b/drivers/clk/thead/clk-th1520-ap.c > @@ -55,6 +55,7 @@ struct ccu_gate { > > struct ccu_div { > u32 enable; > + u32 div_en; > struct ccu_div_internal div; > struct ccu_internal mux; > struct ccu_common common; > @@ -198,6 +199,78 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, > return rate; > } > > +static long ccu_div_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *parent_rate) > +{ > + struct ccu_div *cd = hw_to_ccu_div(hw); > + unsigned int val; > + > + if (!cd->div_en) { > + regmap_read(cd->common.map, cd->common.cfg0, &val); > + val = val >> cd->div.shift; > + val &= GENMASK(cd->div.width - 1, 0); > + return divider_ro_round_rate(hw, rate, parent_rate, > + NULL, cd->div.width, cd->div.flags, > + val); > + } else { > + return divider_round_rate(hw, rate, parent_rate, > + NULL, cd->div.width, cd->div.flags); > + } > +} The round_rate clk op is deprecated. Please convert this over to use determine_rate. Brian