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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7fc15c83bbasm12882885a.60.2025.08.28.10.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 10:04:48 -0700 (PDT) Date: Thu, 28 Aug 2025 13:04:46 -0400 From: Brian Masney To: Ryan.Wanner@microchip.com Cc: mturquette@baylibre.com, sboyd@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, varshini.rajendran@microchip.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh@kernel.org Subject: Re: [PATCH v3 04/32] clk: at91: clk-sam9x60-pll: use clk_parent_data Message-ID: References: <2e7902b73fa6bb5bc8698b3ca0fa7cef583b76f5.1752176711.git.Ryan.Wanner@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2e7902b73fa6bb5bc8698b3ca0fa7cef583b76f5.1752176711.git.Ryan.Wanner@microchip.com> User-Agent: Mutt/2.2.14 (2025-02-20) On Thu, Jul 10, 2025 at 01:06:57PM -0700, Ryan.Wanner@microchip.com wrote: > From: Claudiu Beznea > > Use struct clk_parent_data instead of struct parent_hw as this leads > to less usage of __clk_get_hw() in SoC specific clock drivers and simpler > conversion of existing SoC specific clock drivers from parent_names to > modern clk_parent_data structures. As clk-sam9x60-pll need to know > parent's rate at initialization we pass it now from SoC specific drivers. > This will lead in the end at removing __clk_get_hw() in SoC specific > drivers (that will be solved by subsequent commits). > > Signed-off-by: Claudiu Beznea > [ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set.] > Signed-off-by: Ryan Wanner > --- > drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- > drivers/clk/at91/pmc.h | 5 +++-- > drivers/clk/at91/sam9x60.c | 8 +++++--- > drivers/clk/at91/sam9x7.c | 17 ++++++++++++----- > drivers/clk/at91/sama7d65.c | 16 +++++++++++----- > drivers/clk/at91/sama7g5.c | 17 ++++++++++++----- > 6 files changed, 48 insertions(+), 29 deletions(-) > > diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c > index cefd9948e103..03a7d00dcc6d 100644 > --- a/drivers/clk/at91/clk-sam9x60-pll.c > +++ b/drivers/clk/at91/clk-sam9x60-pll.c > @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = { > > struct clk_hw * __init > sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, > - const char *name, const char *parent_name, > - struct clk_hw *parent_hw, u8 id, > + const char *name, const struct clk_parent_data *parent_data, > + unsigned long parent_rate, u8 id, > const struct clk_pll_characteristics *characteristics, > const struct clk_pll_layout *layout, u32 flags) > { > struct sam9x60_frac *frac; > struct clk_hw *hw; > struct clk_init_data init = {}; > - unsigned long parent_rate, irqflags; > + unsigned long irqflags; > unsigned int val; > int ret; > > - if (id > PLL_MAX_ID || !lock || !parent_hw) > + if (id > PLL_MAX_ID || !lock || !parent_data) > return ERR_PTR(-EINVAL); > > frac = kzalloc(sizeof(*frac), GFP_KERNEL); > @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, > return ERR_PTR(-ENOMEM); > > init.name = name; > - if (parent_name) > - init.parent_names = &parent_name; > - else > - init.parent_hws = (const struct clk_hw **)&parent_hw; > + init.parent_data = (const struct clk_parent_data *)parent_data; > init.num_parents = 1; > if (flags & CLK_SET_RATE_GATE) > init.ops = &sam9x60_frac_pll_ops; > @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, > * its rate leading to enabling this PLL with unsupported > * rate. This will lead to PLL not being locked at all. > */ > - parent_rate = clk_hw_get_rate(parent_hw); > if (!parent_rate) { > hw = ERR_PTR(-EINVAL); > goto free; > diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h > index 63d4c425bed5..b43f6652417f 100644 > --- a/drivers/clk/at91/pmc.h > +++ b/drivers/clk/at91/pmc.h > @@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, > > struct clk_hw * __init > sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, > - const char *name, const char *parent_name, > - struct clk_hw *parent_hw, u8 id, > + const char *name, > + const struct clk_parent_data *parent_data, > + unsigned long parent_rate, u8 id, > const struct clk_pll_characteristics *characteristics, > const struct clk_pll_layout *layout, u32 flags); > > diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c > index db6db9e2073e..fd53e54abf88 100644 > --- a/drivers/clk/at91/sam9x60.c > +++ b/drivers/clk/at91/sam9x60.c > @@ -240,7 +240,8 @@ static void __init sam9x60_pmc_setup(struct device_node *np) > sam9x60_pmc->chws[PMC_MAIN] = hw; > > hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", > - "mainck", sam9x60_pmc->chws[PMC_MAIN], > + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]), > + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]), > 0, &plla_characteristics, > &pll_frac_layout, > /* > @@ -266,8 +267,9 @@ static void __init sam9x60_pmc_setup(struct device_node *np) > sam9x60_pmc->chws[PMC_PLLACK] = hw; > > hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", > - "main_osc", main_osc_hw, 1, > - &upll_characteristics, > + &AT91_CLK_PD_HW(main_osc_hw), > + clk_hw_get_rate(main_osc_hw), > + 1, &upll_characteristics, > &pll_frac_layout, CLK_SET_RATE_GATE); > if (IS_ERR(hw)) > goto err_free; > diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c > index 31184e11165a..edd5fd3a1fa5 100644 > --- a/drivers/clk/at91/sam9x7.c > +++ b/drivers/clk/at91/sam9x7.c > @@ -739,6 +739,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) > { > struct clk_range range = CLK_RANGE(0, 0); > const char *main_xtal_name = "main_xtal"; > + u8 main_xtal_index = 2; Is there a #define somewhere that can be used instead of 2? Or a comment at least? This applies to the other file as well. Brian