[PATCH 0/8] qcom: Refactor sa8775p/qcs9100 based ride boards

[PATCH 0/8] qcom: Refactor sa8775p/qcs9100 based ride boards

[Wasim Nazir]

This series redefine DT structure for sa8775p/qcs9100 based ride/ride-r3
boards by introducing SOM for sa8775p, qcs9100.
It also introduces ethernet dtsi with two variants of capabilities.
It also refactor all common parts of ride boards to ride-common dtsi.

Below are detailed explaination on each type of HW variants supported:

# Ride HW information
-----------------------------
Ride is a modular hardware system with several smaller daughter cards
connected to single backplane board and each daughter card is stacked on
top of each other. I will try to explain each daughter card with HW
components and how it is connected to construct the ride-hw.

Backplane board:
  - It contains an MCU (Aurix TC397), CAN/LIN transceiver,
    Audio/GNSS/IMU-I2C signals, Fan header
  - It holds & connects all the daughter cards.

SOC card:
  - It contains:
    - SOM:
      - One of QCS9100M/QAM8775p SOM.
      - Each SOM is composed of either qcs9100/sa8775p SOC,
        along with DDR & PMICs.
      - Each SOM can be mounted to same SOC-daughter card of ride-hw.
    - In addition to SOM, it also has
      - 4x UART, 2x USB 3.1 & 1x USB 2.0
      - Memory: 1x OSPI, 2x UFS-3.1
      - Debug: JTAG/QDSS header
      - PCIe0, PCIe1 & Display signals
      - Reset button
  - It is connected to backplain board via B2B connector.

Display card:
  - It contains:
    - 4 eDP ports & 2 DSI-DP bridge
    - I2C GPIO expander & I2C switch
  - It is connected to SOC-card via B2B connector.

Camera card:
  - It contains:
    - 4 Quad DE-serializer, each supporting 4 MIPI CSI inputs
    - Total upto 16 Cameras ports are supported.
  - It is connected to backplain board via B2B connector.

Ethernet card:
  - There are two variants of ethernet card each with different capabilities:
    - [Ethernet-v1] card contains:
      - 2x 1G RGMII phy, 2x 1G SGMII phy(enabled currently)
      - Total 4 phy supported, only 2 phy are enabled and it is used in ride.
    - [Ethernet-v2] card contains:
      - 2x 1G RGMII phy, 2x 2.5G HSGMII(enabled currently) & 10G PCIe
        based MAC+PHY controller
      - Total 5 phy supported, only 2 phy are enabled and it is used
        in ride-r3.
  - Either [Ethernet-v1] or [Ethernet-v2] is connected to backplain
    board via B2B connector.

PCIe card:
  - It contains:
    - PCIe connections to SOC-card
    - NVME, 2x WLBT module QCA6696/QCA6698 (Wi-Fi & bluetooth solution)
      & GNSS module
  - It is connected to backplain board via B2B connector & PCIe signals
    are connected to SOC card via flyover cables.

Sensor Card:
  - It contains 3-Axix compass & 6-Axis 3D IMU (accel/gyro) module which
    are communicating via I2C
  - It is connected to backplain board via B2B connector.

Front panel card:
  - It does not contain any active circuitry, only ports are available
    - Audio-in/out ports
    - USB hub ports
    - CAN/LIN ports
    - 12V power off switch
  - It is connected to backplain board via ribbon cable.


Considering outlined h/w description, following are ride configuration
variation each platform supporting:

Between qcs9100 & sa8775p ride/ride-r3 boards, SOM is changing; And between
ride & ride-r3 ethernet is changing.
Excluding these differences all other cards i.e SOC, display, camera,
PCIe, sensor, front & backplain are same and are refactored in ride-common.
If any variant of these cards comes up in future we need to refactor
ride-common accordingly.

Since we don't have a document yet which formally describes qcs9100 ride
board with [Ethernet-v1] card, I am removing the board and we can re-enable
after complete documentation is available.

Considering current outlines of all daughter cards, following defines
ride/ride-r3 variant boards:
  - sa8775p ride    : QAM8775p SOM + [Ethernet-v1] + other daughter cards
  - sa8775p ride-r3 : QAM8775p SOM + [Ethernet-v2] + other daughter cards
  - qcs9100 ride-r3 : QCS9100M SOM + [Ethernet-v2] + other daughter cards

Below is the pictorial diagram for updated DT structure depicting all our HW.
- SOM dtsi:
  - qam8775p-som.dtsi specifying sa8775p based SOM having SOC, PMICs,
    Memory-map.
  - qcs9100-som.dtsi specifying QCS9100M based SOM having SOC, PMICs, Memory-map
    updates.
- sa8775p-ride-common.dtsi specifying ride common daughter cards for all ride
  boards. This include SOC-card, display, camera, PCIe, sensor, front &
  backplain cards.
- Ethernet variants dtsi:
  - sa8775p-ride-ethernet-88ea1512.dtsi specifying ethernet card which
    uses 2x 1G - SGMII (Marvell 88EA1512-B2) phy in Main-domain
  - sa8775p-ride-ethernet-aqr115c.dtsi specifying ethernet card which
    uses 2x 2.5G - HSGMII (Marvell AQR115c) phy in Main-domain

+---------------------------------------------------------------------------------------------------+
|                                                                                                   |
|                        sa8775p.dtsi                                                               |
|                             |                                                                     |
|                 +-----------------------+                                                         |
|                 |                       |                                                         |
|                 v                       v                                                         |
|          qam8775p-som.dtsi        qcs9100-som.dtsi                                                |
|                 |                       |                                                         |
|                 v                       v                                                         |
|              (AUTO)                   (IOT)                                                       |
|                 |                       |                                                         |
|                 |                       |                                                         |
|                 |                       |                                                         |
|                 | +-----------------------+---------------< sa8775p-ride-ethernet-aqr115c.dtsi    |
|                 | |                     | |                                                       |
|                 | | +-----------------------+----------+--< sa8775p-ride-common.dtsi              |
|                 | | |                   | | |          |                                          |
|       +---------+ | |                   | | |          |                                          |
|       |         | | |                   | | |          |                                          |
|       |         v v v                   v v v          |                                          |
|       |   sa8775p-ride-r3.dts    qcs9100-ride-r3.dts   |                                          |
|       |                                                |                                          |
|       | +----------------------------------------------+                                          |
|       | |                                                                                         |
|       | | +------------------------------------------------< sa8775p-ride-ethernet-88ea1512.dtsi  |
|       | | |                                                                                       |
|       v v v                                                                                       |
| sa8775p-ride.dts                                                                                  |
|                                                                                                   |
+---------------------------------------------------------------------------------------------------+

This series provides code refactoring changes for sa8775p/qcs9100
ride/ride-r3 boards from previous discussion [1] excluding any new
features or boards.

No functional impact, and it is verified with comparing decompiled DTB
(dtx_diff and fdtdump+diff).
The only difference is that *-som compatibility has been added in all boards
and qcs9100-ride board is removed.

[1] https://lore.kernel.org/all/20241229152332.3068172-1-quic_wasimn@quicinc.com/

---

Wasim Nazir (8):
  dt-bindings: arm: qcom: Remove bindings for qcs9100 ride
  arm64: dts: qcom: qcs9100: Remove qcs9100 ride board
  arm64: dts: qcom: sa8775p: Add ethernet card for ride & ride-r3
  arm64: dts: qcom: sa8775p: Create ride common file
  dt-bindings: arm: qcom: Add bindings for qam8775p SOM
  arm64: dts: qcom: sa8775p: Introduce QAM8775p SOM
  dt-bindings: arm: qcom: Add bindings for QCS9100M SOM
  arm64: dts: qcom: qcs9100: Introduce QCS9100M SOM

 .../devicetree/bindings/arm/qcom.yaml         |   3 +-
 arch/arm64/boot/dts/qcom/Makefile             |   1 -
 arch/arm64/boot/dts/qcom/qam8775p-som.dtsi    |   9 +
 arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts  |  10 +-
 arch/arm64/boot/dts/qcom/qcs9100-ride.dts     |  11 -
 arch/arm64/boot/dts/qcom/qcs9100-som.dtsi     |   9 +
 ...75p-ride.dtsi => sa8775p-ride-common.dtsi} | 169 +--------------
 .../qcom/sa8775p-ride-ethernet-88ea1512.dtsi  | 205 ++++++++++++++++++
 .../qcom/sa8775p-ride-ethernet-aqr115c.dtsi   | 205 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts  |  42 +---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts     |  42 +---
 11 files changed, 450 insertions(+), 256 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/qam8775p-som.dtsi
 delete mode 100644 arch/arm64/boot/dts/qcom/qcs9100-ride.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
 rename arch/arm64/boot/dts/qcom/{sa8775p-ride.dtsi => sa8775p-ride-common.dtsi} (86%)
 create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-88ea1512.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-aqr115c.dtsi


base-commit: 33035b665157558254b3c21c3f049fd728e72368
--
2.49.0

[PATCH 1/8] dt-bindings: arm: qcom: Remove bindings for qcs9100 ride

[Wasim Nazir]

Remove qcs9100 ride support as HW is not formulated yet.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 08c329b1e919..96420c02a800 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -962,7 +962,6 @@ properties:

       - items:
           - enum:
-              - qcom,qcs9100-ride
               - qcom,qcs9100-ride-r3
           - const: qcom,qcs9100
           - const: qcom,sa8775p
--
2.49.0

[PATCH 2/8] arm64: dts: qcom: qcs9100: Remove qcs9100 ride board

[Wasim Nazir]

Remove qcs9100 ride support as HW is not formulated yet.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile         |  1 -
 arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 11 -----------
 2 files changed, 12 deletions(-)
 delete mode 100644 arch/arm64/boot/dts/qcom/qcs9100-ride.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index adb4d026bcc4..162d9c1b5a0f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -122,7 +122,6 @@ qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vis
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-vision-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
-dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qrb2210-rb1.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts
deleted file mode 100644
index 979462dfec30..000000000000
--- a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-/dts-v1/;
-
-#include "sa8775p-ride.dts"
-/ {
-	model = "Qualcomm QCS9100 Ride";
-	compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";
-};
--
2.49.0

[PATCH 3/8] arm64: dts: qcom: sa8775p: Add ethernet card for ride & ride-r3

[Wasim Nazir]

Add separate ethernet card with 1G & 2.5G phy capabilities respectively.
  *-88ea1512.dtsi is for 2x 1G - SGMII (Marvell 88EA1512-B2) phy
  *-aqr115c.dtsi is for 2x 2.5G - HSGMII (Marvell AQR115c) phy

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 .../qcom/sa8775p-ride-ethernet-88ea1512.dtsi  | 205 ++++++++++++++++++
 .../qcom/sa8775p-ride-ethernet-aqr115c.dtsi   | 205 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts  |  36 +--
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts     |  36 +--
 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi    | 163 --------------
 5 files changed, 414 insertions(+), 231 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-88ea1512.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-aqr115c.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-88ea1512.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-88ea1512.dtsi
new file mode 100644
index 000000000000..28102b9a7dd5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-88ea1512.dtsi
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/*
+ * Ethernet card for sa8775p based ride boards.
+ * It supports 2x 1G - SGMII (Marvell 88EA1512-B2) phy for Main domain
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	aliases {
+		ethernet0 = &ethernet0;
+		ethernet1 = &ethernet1;
+	};
+};
+
+&tlmm {
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio8";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio9";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+};
+
+&ethernet0 {
+	phy-handle = <&sgmii_phy0>;
+	phy-mode = "sgmii";
+
+	pinctrl-0 = <&ethernet0_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,ps-speed = <1000>;
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sgmii_phy0: phy@8 {
+			compatible = "ethernet-phy-id0141.0dd4";
+			reg = <0x8>;
+			device_type = "ethernet-phy";
+			interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+
+		sgmii_phy1: phy@a {
+			compatible = "ethernet-phy-id0141.0dd4";
+			reg = <0xa>;
+			device_type = "ethernet-phy";
+			interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&ethernet1 {
+	phy-handle = <&sgmii_phy1>;
+	phy-mode = "sgmii";
+
+	snps,mtl-rx-config = <&mtl_rx_setup1>;
+	snps,mtl-tx-config = <&mtl_tx_setup1>;
+	snps,ps-speed = <1000>;
+
+	status = "okay";
+
+	mtl_rx_setup1: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup1: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-aqr115c.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-aqr115c.dtsi
new file mode 100644
index 000000000000..98c3368f3ae8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-ethernet-aqr115c.dtsi
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/*
+ * Ethernet card for sa8775p based ride r3 boards.
+ * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	aliases {
+		ethernet0 = &ethernet0;
+		ethernet1 = &ethernet1;
+	};
+};
+
+&tlmm {
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio8";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio9";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+};
+
+&ethernet0 {
+	phy-handle = <&hsgmii_phy0>;
+	phy-mode = "2500base-x";
+
+	pinctrl-0 = <&ethernet0_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,ps-speed = <1000>;
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hsgmii_phy0: phy@8 {
+			compatible = "ethernet-phy-id31c3.1c33";
+			reg = <0x8>;
+			device_type = "ethernet-phy";
+			interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+
+		hsgmii_phy1: phy@0 {
+			compatible = "ethernet-phy-id31c3.1c33";
+			reg = <0x0>;
+			device_type = "ethernet-phy";
+			interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&ethernet1 {
+	phy-handle = <&hsgmii_phy1>;
+	phy-mode = "2500base-x";
+
+	snps,mtl-rx-config = <&mtl_rx_setup1>;
+	snps,mtl-tx-config = <&mtl_tx_setup1>;
+	snps,ps-speed = <1000>;
+
+	status = "okay";
+
+	mtl_rx_setup1: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup1: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
index ae065ae92478..3e2aa34763ee 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
@@ -1,47 +1,15 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
  * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
  */

 /dts-v1/;

 #include "sa8775p-ride.dtsi"
+#include "sa8775p-ride-ethernet-aqr115c.dtsi"

 / {
 	model = "Qualcomm SA8775P Ride Rev3";
 	compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p";
 };
-
-&ethernet0 {
-	phy-mode = "2500base-x";
-};
-
-&ethernet1 {
-	phy-mode = "2500base-x";
-};
-
-&mdio {
-	compatible = "snps,dwmac-mdio";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	sgmii_phy0: phy@8 {
-		compatible = "ethernet-phy-id31c3.1c33";
-		reg = <0x8>;
-		device_type = "ethernet-phy";
-		interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <11000>;
-		reset-deassert-us = <70000>;
-	};
-
-	sgmii_phy1: phy@0 {
-		compatible = "ethernet-phy-id31c3.1c33";
-		reg = <0x0>;
-		device_type = "ethernet-phy";
-		interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <11000>;
-		reset-deassert-us = <70000>;
-	};
-};
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 2e87fd760dbd..4e77178cf66b 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -1,47 +1,15 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
  * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
  */

 /dts-v1/;

 #include "sa8775p-ride.dtsi"
+#include "sa8775p-ride-ethernet-88ea1512.dtsi"

 / {
 	model = "Qualcomm SA8775P Ride";
 	compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
 };
-
-&ethernet0 {
-	phy-mode = "sgmii";
-};
-
-&ethernet1 {
-	phy-mode = "sgmii";
-};
-
-&mdio {
-	compatible = "snps,dwmac-mdio";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	sgmii_phy0: phy@8 {
-		compatible = "ethernet-phy-id0141.0dd4";
-		reg = <0x8>;
-		device_type = "ethernet-phy";
-		interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <11000>;
-		reset-deassert-us = <70000>;
-	};
-
-	sgmii_phy1: phy@a {
-		compatible = "ethernet-phy-id0141.0dd4";
-		reg = <0xa>;
-		device_type = "ethernet-phy";
-		interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <11000>;
-		reset-deassert-us = <70000>;
-	};
-};
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
index 967913169539..04f02572a96b 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
@@ -13,8 +13,6 @@

 / {
 	aliases {
-		ethernet0 = &ethernet0;
-		ethernet1 = &ethernet1;
 		i2c11 = &i2c11;
 		i2c18 = &i2c18;
 		serial0 = &uart10;
@@ -361,151 +359,6 @@ vreg_l8e: ldo8 {
 	};
 };

-&ethernet0 {
-	phy-handle = <&sgmii_phy0>;
-
-	pinctrl-0 = <&ethernet0_default>;
-	pinctrl-names = "default";
-
-	snps,mtl-rx-config = <&mtl_rx_setup>;
-	snps,mtl-tx-config = <&mtl_tx_setup>;
-	snps,ps-speed = <1000>;
-
-	status = "okay";
-
-	mdio: mdio {
-		compatible = "snps,dwmac-mdio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	mtl_rx_setup: rx-queues-config {
-		snps,rx-queues-to-use = <4>;
-		snps,rx-sched-sp;
-
-		queue0 {
-			snps,dcb-algorithm;
-			snps,map-to-dma-channel = <0x0>;
-			snps,route-up;
-			snps,priority = <0x1>;
-		};
-
-		queue1 {
-			snps,dcb-algorithm;
-			snps,map-to-dma-channel = <0x1>;
-			snps,route-ptp;
-		};
-
-		queue2 {
-			snps,avb-algorithm;
-			snps,map-to-dma-channel = <0x2>;
-			snps,route-avcp;
-		};
-
-		queue3 {
-			snps,avb-algorithm;
-			snps,map-to-dma-channel = <0x3>;
-			snps,priority = <0xc>;
-		};
-	};
-
-	mtl_tx_setup: tx-queues-config {
-		snps,tx-queues-to-use = <4>;
-
-		queue0 {
-			snps,dcb-algorithm;
-		};
-
-		queue1 {
-			snps,dcb-algorithm;
-		};
-
-		queue2 {
-			snps,avb-algorithm;
-			snps,send_slope = <0x1000>;
-			snps,idle_slope = <0x1000>;
-			snps,high_credit = <0x3e800>;
-			snps,low_credit = <0xffc18000>;
-		};
-
-		queue3 {
-			snps,avb-algorithm;
-			snps,send_slope = <0x1000>;
-			snps,idle_slope = <0x1000>;
-			snps,high_credit = <0x3e800>;
-			snps,low_credit = <0xffc18000>;
-		};
-	};
-};
-
-&ethernet1 {
-	phy-handle = <&sgmii_phy1>;
-
-	snps,mtl-rx-config = <&mtl_rx_setup1>;
-	snps,mtl-tx-config = <&mtl_tx_setup1>;
-	snps,ps-speed = <1000>;
-
-	status = "okay";
-
-	mtl_rx_setup1: rx-queues-config {
-		snps,rx-queues-to-use = <4>;
-		snps,rx-sched-sp;
-
-		queue0 {
-			snps,dcb-algorithm;
-			snps,map-to-dma-channel = <0x0>;
-			snps,route-up;
-			snps,priority = <0x1>;
-		};
-
-		queue1 {
-			snps,dcb-algorithm;
-			snps,map-to-dma-channel = <0x1>;
-			snps,route-ptp;
-		};
-
-		queue2 {
-			snps,avb-algorithm;
-			snps,map-to-dma-channel = <0x2>;
-			snps,route-avcp;
-		};
-
-		queue3 {
-			snps,avb-algorithm;
-			snps,map-to-dma-channel = <0x3>;
-			snps,priority = <0xc>;
-		};
-	};
-
-	mtl_tx_setup1: tx-queues-config {
-		snps,tx-queues-to-use = <4>;
-
-		queue0 {
-			snps,dcb-algorithm;
-		};
-
-		queue1 {
-			snps,dcb-algorithm;
-		};
-
-		queue2 {
-			snps,avb-algorithm;
-			snps,send_slope = <0x1000>;
-			snps,idle_slope = <0x1000>;
-			snps,high_credit = <0x3e800>;
-			snps,low_credit = <0xffc18000>;
-		};
-
-		queue3 {
-			snps,avb-algorithm;
-			snps,send_slope = <0x1000>;
-			snps,idle_slope = <0x1000>;
-			snps,high_credit = <0x3e800>;
-			snps,low_credit = <0xffc18000>;
-		};
-	};
-};
-
 &i2c11 {
 	clock-frequency = <400000>;
 	pinctrl-0 = <&qup_i2c11_default>;
@@ -696,22 +549,6 @@ dp1_hot_plug_det: dp1-hot-plug-det-state {
 		bias-disable;
 	};

-	ethernet0_default: ethernet0-default-state {
-		ethernet0_mdc: ethernet0-mdc-pins {
-			pins = "gpio8";
-			function = "emac0_mdc";
-			drive-strength = <16>;
-			bias-pull-up;
-		};
-
-		ethernet0_mdio: ethernet0-mdio-pins {
-			pins = "gpio9";
-			function = "emac0_mdio";
-			drive-strength = <16>;
-			bias-pull-up;
-		};
-	};
-
 	qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
--
2.49.0

[PATCH 4/8] arm64: dts: qcom: sa8775p: Create ride common file

[Wasim Nazir]

Ride/Ride-r3 board used with sa8775p & its derivative SOCs:
  - Is based on multiple daughter cards (SOC-card, display, camera,
    ethernet, pcie, sensor, front & backplain, etc.).
  - Across sa8775p & its derivative SOCs, SOM is changing.
  - Across Ride & Ride-r3 board, ethernet card is changing.

Excluding the differences all other cards i.e SOC-card, display, camera,
PCIe, sensor, front & backplain are same across Ride/Ride-r3 boards
used with sa8775p & its derivative SOCs and are refactored to ride-common.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 .../qcom/{sa8775p-ride.dtsi => sa8775p-ride-common.dtsi}    | 6 +-----
 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts                | 5 ++++-
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts                   | 5 ++++-
 3 files changed, 9 insertions(+), 7 deletions(-)
 rename arch/arm64/boot/dts/qcom/{sa8775p-ride.dtsi => sa8775p-ride-common.dtsi} (99%)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride-common.dtsi
similarity index 99%
rename from arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
rename to arch/arm64/boot/dts/qcom/sa8775p-ride-common.dtsi
index 04f02572a96b..e44f220ae75a 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-common.dtsi
@@ -1,16 +1,12 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
  * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
  */

-/dts-v1/;
-
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>

-#include "sa8775p.dtsi"
-#include "sa8775p-pmics.dtsi"
-
 / {
 	aliases {
 		i2c11 = &i2c11;
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
index 3e2aa34763ee..a9014095daba 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
@@ -6,7 +6,10 @@

 /dts-v1/;

-#include "sa8775p-ride.dtsi"
+#include "sa8775p.dtsi"
+#include "sa8775p-pmics.dtsi"
+
+#include "sa8775p-ride-common.dtsi"
 #include "sa8775p-ride-ethernet-aqr115c.dtsi"

 / {
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 4e77178cf66b..e98554f825d5 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -6,7 +6,10 @@

 /dts-v1/;

-#include "sa8775p-ride.dtsi"
+#include "sa8775p.dtsi"
+#include "sa8775p-pmics.dtsi"
+
+#include "sa8775p-ride-common.dtsi"
 #include "sa8775p-ride-ethernet-88ea1512.dtsi"

 / {
--
2.49.0

[PATCH 5/8] dt-bindings: arm: qcom: Add bindings for qam8775p SOM

[Wasim Nazir]

Add devicetree bindings for QAM8775p SOM which is based on sa8775p SOC.
QAM8775p SOM have sa8775p SOC, PMICs and DDR and it is stacked on
ride/ride-r3 boards.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 96420c02a800..671f2d571260 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -958,6 +958,7 @@ properties:
           - enum:
               - qcom,sa8775p-ride
               - qcom,sa8775p-ride-r3
+          - const: qcom,qam8775p-som
           - const: qcom,sa8775p

       - items:
--
2.49.0

[PATCH 6/8] arm64: dts: qcom: sa8775p: Introduce QAM8775p SOM

[Wasim Nazir]

qam8775p-som.dtsi specifies SA8775p based SOM having SOC, PMICs & DDR.
sa8775p-ride & sa8775p-ride-r3 boards are based on QAM8775p SOM.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qam8775p-som.dtsi   | 9 +++++++++
 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 5 ++---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts    | 5 ++---
 3 files changed, 13 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/qam8775p-som.dtsi

diff --git a/arch/arm64/boot/dts/qcom/qam8775p-som.dtsi b/arch/arm64/boot/dts/qcom/qam8775p-som.dtsi
new file mode 100644
index 000000000000..92adebb2e18f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qam8775p-som.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sa8775p.dtsi"
+#include "sa8775p-pmics.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
index a9014095daba..f75e92e05bcd 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
@@ -6,13 +6,12 @@

 /dts-v1/;

-#include "sa8775p.dtsi"
-#include "sa8775p-pmics.dtsi"
+#include "qam8775p-som.dtsi"

 #include "sa8775p-ride-common.dtsi"
 #include "sa8775p-ride-ethernet-aqr115c.dtsi"

 / {
 	model = "Qualcomm SA8775P Ride Rev3";
-	compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p";
+	compatible = "qcom,sa8775p-ride-r3", "qcom,qam8775p-som", "qcom,sa8775p";
 };
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index e98554f825d5..568eff8c1999 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -6,13 +6,12 @@

 /dts-v1/;

-#include "sa8775p.dtsi"
-#include "sa8775p-pmics.dtsi"
+#include "qam8775p-som.dtsi"

 #include "sa8775p-ride-common.dtsi"
 #include "sa8775p-ride-ethernet-88ea1512.dtsi"

 / {
 	model = "Qualcomm SA8775P Ride";
-	compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
+	compatible = "qcom,sa8775p-ride", "qcom,qam8775p-som", "qcom,sa8775p";
 };
--
2.49.0

[PATCH 7/8] dt-bindings: arm: qcom: Add bindings for QCS9100M SOM

[Wasim Nazir]

QCS9100 SOC is compatible Industrial-IOT grade variant of SA8775p SOC.

Add devicetree bindings for QCS9100M SOM which is based on qcs9100 SOC.
QCS9100M SOM have qcs9100 SOC, PMICs and DDR along with memory-map
updates and it is stacked on ride-r3 board.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 671f2d571260..514ed617565b 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -964,6 +964,7 @@ properties:
       - items:
           - enum:
               - qcom,qcs9100-ride-r3
+          - const: qcom,qcs9100-som
           - const: qcom,qcs9100
           - const: qcom,sa8775p

--
2.49.0

[PATCH 8/8] arm64: dts: qcom: qcs9100: Introduce QCS9100M SOM

[Wasim Nazir]

qcs9100 SOC is IOT variant of sa8775p SOC and it supports safety
monitoring feature of Safety Island(SAIL) subsystem.
qcs9100-som.dtsi specifies qcs9100 based SOM having SOC, PMICs
& Memory-map updates (not added currently as part of code refactoring).
qcs9100-ride-r3 board is based on QCS9100M SOM.
qcs9100-ride-r3 also supports 2.5G ethernet phy i.e aqr115c.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 10 +++++++---
 arch/arm64/boot/dts/qcom/qcs9100-som.dtsi    |  9 +++++++++
 2 files changed, 16 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9100-som.dtsi

diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
index 759d1ec694b2..aadf9e4a8a05 100644
--- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
@@ -1,11 +1,15 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 /dts-v1/;

-#include "sa8775p-ride-r3.dts"
+#include "qcs9100-som.dtsi"
+
+#include "sa8775p-ride-common.dtsi"
+#include "sa8775p-ride-ethernet-aqr115c.dtsi"
+
 / {
 	model = "Qualcomm QCS9100 Ride Rev3";
-	compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";
+	compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100-som", "qcom,qcs9100", "qcom,sa8775p";
 };
diff --git a/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
new file mode 100644
index 000000000000..92adebb2e18f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sa8775p.dtsi"
+#include "sa8775p-pmics.dtsi"
--
2.49.0

Re: [PATCH 5/8] dt-bindings: arm: qcom: Add bindings for qam8775p SOM

[Krzysztof Kozlowski]

On 07/05/2025 08:51, Wasim Nazir wrote:
> Add devicetree bindings for QAM8775p SOM which is based on sa8775p SOC.

You do not add new bindings. You instead change existing ones without
explanation why making that change.



Best regards,
Krzysztof

Re: [PATCH 6/8] arm64: dts: qcom: sa8775p: Introduce QAM8775p SOM

[Krzysztof Kozlowski]

On 07/05/2025 08:51, Wasim Nazir wrote:
> qam8775p-som.dtsi specifies SA8775p based SOM having SOC, PMICs & DDR.
> sa8775p-ride & sa8775p-ride-r3 boards are based on QAM8775p SOM.
> 
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qam8775p-som.dtsi   | 9 +++++++++
>  arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 5 ++---
>  arch/arm64/boot/dts/qcom/sa8775p-ride.dts    | 5 ++---
>  3 files changed, 13 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/qcom/qam8775p-som.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/qam8775p-som.dtsi b/arch/arm64/boot/dts/qcom/qam8775p-som.dtsi
> new file mode 100644
> index 000000000000..92adebb2e18f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qam8775p-som.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +#include "sa8775p-pmics.dtsi"

That's an empty file. What is the point of it except making everything
more complicated?


Best regards,
Krzysztof

Re: [PATCH 7/8] dt-bindings: arm: qcom: Add bindings for QCS9100M SOM

[Krzysztof Kozlowski]

On 07/05/2025 08:51, Wasim Nazir wrote:
> QCS9100 SOC is compatible Industrial-IOT grade variant of SA8775p SOC.
> 
> Add devicetree bindings for QCS9100M SOM which is based on qcs9100 SOC.

Compatible says QCS9100, not QCS9100M.

> QCS9100M SOM have qcs9100 SOC, PMICs and DDR along with memory-map
> updates and it is stacked on ride-r3 board.

I do not see any point of this patch. You just change existing bindings
based on what? New product? But this was already released, so how can
the hardware change?

Best regards,
Krzysztof

Re: [PATCH 8/8] arm64: dts: qcom: qcs9100: Introduce QCS9100M SOM

[Krzysztof Kozlowski]

On 07/05/2025 08:51, Wasim Nazir wrote:
> diff --git a/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
> new file mode 100644
> index 000000000000..92adebb2e18f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs9100-som.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +#include "sa8775p-pmics.dtsi"

Again pointless file - it brings no benefits, no contents, just making
everything more complicated to follow, more includes and indirections.

Best regards,
Krzysztof

Re: [PATCH 0/8] qcom: Refactor sa8775p/qcs9100 based ride boards

[Andrew Lunn]

> Ethernet card:
>   - There are two variants of ethernet card each with different capabilities:
>     - [Ethernet-v1] card contains:
>       - 2x 1G RGMII phy, 2x 1G SGMII phy(enabled currently)
>       - Total 4 phy supported, only 2 phy are enabled and it is used in ride.
>     - [Ethernet-v2] card contains:
>       - 2x 1G RGMII phy, 2x 2.5G HSGMII(enabled currently) & 10G PCIe
>         based MAC+PHY controller
>       - Total 5 phy supported, only 2 phy are enabled and it is used
>         in ride-r3.
>   - Either [Ethernet-v1] or [Ethernet-v2] is connected to backplain
>     board via B2B connector.

Is it possible to identify the card, e.g. does it have an I2C EEPROM,
or some strapping resistors on the B2B bus?

I'm just wondering if DT overlays would be a better solution.

	Andrew

Re: [PATCH 3/8] arm64: dts: qcom: sa8775p: Add ethernet card for ride & ride-r3

[Andrew Lunn]

> +&ethernet0 {
> +	phy-handle = <&sgmii_phy0>;
> +	phy-mode = "sgmii";
> +
> +	pinctrl-0 = <&ethernet0_default>;
> +	pinctrl-names = "default";
> +
> +	snps,mtl-rx-config = <&mtl_rx_setup>;
> +	snps,mtl-tx-config = <&mtl_tx_setup>;
> +	snps,ps-speed = <1000>;

SGMII can only go up to 1000, so why is this property needed?

> +&ethernet0 {
> +	phy-handle = <&hsgmii_phy0>;
> +	phy-mode = "2500base-x";
> +
> +	pinctrl-0 = <&ethernet0_default>;
> +	pinctrl-names = "default";
> +
> +	snps,mtl-rx-config = <&mtl_rx_setup>;
> +	snps,mtl-tx-config = <&mtl_tx_setup>;
> +	snps,ps-speed = <1000>;

This looks odd. 2500Base-X, yet 1000?

	Andrew

Re: [PATCH 5/8] dt-bindings: arm: qcom: Add bindings for qam8775p SOM

[Wasim Nazir]

On Wed, May 07, 2025 at 09:00:18AM +0200, Krzysztof Kozlowski wrote:
> On 07/05/2025 08:51, Wasim Nazir wrote:
> > Add devicetree bindings for QAM8775p SOM which is based on sa8775p SOC.
> 
> You do not add new bindings. You instead change existing ones without
> explanation why making that change.
> 

I understand your concern. We thought of adding it to define the SOM HW
which was not done earlier.
I will drop all the SOM bindings and maintain only SOM DT structure on
IQ9 target (qcs9100), which we need it to add memory-map updates.

Also, I will drop similar change from IQ-9075-evk series [1] for maintaining
similar dt-bindings for IQ9 (qcs9100 & qcs9075) series of targets.

[1]
https://lore.kernel.org/all/20250429054906.113317-1-quic_wasimn@quicinc.com/

> 
> 
> Best regards,
> Krzysztof

Regards,
Wasim

Re: [PATCH 3/8] arm64: dts: qcom: sa8775p: Add ethernet card for ride & ride-r3

[Mohd Ayaan Anwar]

On Wed, May 07, 2025 at 04:23:52PM +0200, Andrew Lunn wrote:
> > +&ethernet0 {
> > +	phy-handle = <&sgmii_phy0>;
> > +	phy-mode = "sgmii";
> > +
> > +	pinctrl-0 = <&ethernet0_default>;
> > +	pinctrl-names = "default";
> > +
> > +	snps,mtl-rx-config = <&mtl_rx_setup>;
> > +	snps,mtl-tx-config = <&mtl_tx_setup>;
> > +	snps,ps-speed = <1000>;
> 
> SGMII can only go up to 1000, so why is this property needed?
> 

That's true. This shouldn't be required.

> > +&ethernet0 {
> > +	phy-handle = <&hsgmii_phy0>;
> > +	phy-mode = "2500base-x";
> > +
> > +	pinctrl-0 = <&ethernet0_default>;
> > +	pinctrl-names = "default";
> > +
> > +	snps,mtl-rx-config = <&mtl_rx_setup>;
> > +	snps,mtl-tx-config = <&mtl_tx_setup>;
> > +	snps,ps-speed = <1000>;
> 
> This looks odd. 2500Base-X, yet 1000?
> 
> 	Andrew

Just to give some background, this board is using the infamous OCSGMII
mode. But you are correct, the "snps,ps-speed" property is not required
here. The qcom-ethqos driver is agnostic to it as the MAC speed is set
using PCS AN during mac_link_up:
stmmac_mac_link_up -> fix_mac_speed -> ethqos_configure_sgmii.

We will remove it in the next revision of [0]. I also noticed this
redundant property in a few other places and will submit separate
cleanup patches for those as well.

	Ayaan
---
[0] https://lore.kernel.org/all/20250826-lemans-evk-bu-v1-3-08016e0d3ce5@oss.qualcomm.com/