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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-373ba2739ccsm5012481fa.10.2025.10.02.00.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 00:56:34 -0700 (PDT) Date: Thu, 2 Oct 2025 09:56:32 +0200 From: Marcus Folkesson To: Ian Ray Cc: Support Opensource , Lee Jones , Axel Lin , Adam Thomson , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] mfd: da9052-spi: change read-mask to write-mask Message-ID: References: <20240925-da9052-v2-1-f243e4505b07@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="fALL9UhP4IJsq69l" Content-Disposition: inline In-Reply-To: --fALL9UhP4IJsq69l Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hello Ian, On Thu, Oct 02, 2025 at 10:49:32AM +0300, Ian Ray wrote: > On Thu, Oct 02, 2025 at 09:23:21AM +0200, Marcus Folkesson wrote: > > Hello Ian, > >=20 > > On Wed, Oct 01, 2025 at 04:03:37PM +0300, Ian Ray wrote: > > > Hello Marcus, > > >=20 > > > On Wed, Sep 25, 2024 at 12:19:53PM +0200, Marcus Folkesson wrote: > > > > Driver has mixed up the R/W bit. > > > > The LSB bit is set on write rather than read. > > > > Change it to avoid nasty things to happen. > > > >=20 > > > > Fixes: e9e9d3973594 ("mfd: da9052: Avoid setting read_flag_mask for= da9052-i2c driver") > > > > Signed-off-by: Marcus Folkesson > > >=20 > > > Your patch breaks DA9053 SPI communication (for me, at least) on the > > > 6.1.y branch (I have not tested on master). > > >=20 > > > The datasheets [1] and [2] both refer to R/Wn in the SPI signalling. > > >=20 > > > What led to the assertion that "The LSB bit is set on write rather > > > than read."? > > >=20 > > > In the original code "config.read_flag_mask =3D 1;", is OR'd into the > > > buffer in regmap_set_work_buf_flag_mask. This sets the "R" bit as > > > expected. > >=20 > > Hrm. > >=20 > > I follow you and agree with what you say. > > Could you please read out R19 INTERFACE register? > > Bit 3, R/W POL, deviates from the default value (1) in my setup, which > > is probably the reason why it doesn't work for me without the patch. >=20 > -- >8 --=20 > # cat /sys/kernel/debug/regmap/spi2.0/registers |grep "^13:" > 13: 88 > -- >8 --=20 >=20 > >=20 > > Your datasheet revision is later than mine, could you plese verify that > > the default value is still 1 for DA9052 in your revision? >=20 > Yes it is still 1 (the complete set of defaults for R19 is 10011000). >=20 > >=20 > > If that is the case, either the datasheet is wrong or my chips must > > somehow been preloaded with some values. >=20 > Yes, in my understanding these PMICs are highly configurable via OTP. > (Almost every register can be customized.) >=20 > >=20 > > As nobody else has reported any issue I guess it is safer to revert > > this patch. >=20 > Agree -- following the datasheet default is probably the right thing to > do here. >=20 > For the future, we could consider an optional device tree property to > describe this read/write bit polarity. Yes, I'm actually working on a patch for this, I will send it out shortly. >=20 > Thanks, > Ian >=20 > >=20 > > >=20 > > > [1] DA9052 CFR0011-120-00 Rev 5, Revision 2.5, 13-Feb-2017, page 67. > > > [2] DA9053 DA9053-00-IDS2n_131017, page 54. > > >=20 > > > Blue skies, > > > Ian > >=20 > >=20 > > Best regards, > > Marcus Folkesson Best regards, Marcus Folkesson --fALL9UhP4IJsq69l Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEEBVGi6LZstU1kwSxliIBOb1ldUjIFAmjeMCgACgkQiIBOb1ld UjIMEA/8DD8DLsYdTX5OUX1f0IHA9/8s0DWhIb2D9iMjw6aqocfv7ZSaF4d092BH snRPXvH3B10SFBCKa8FTCKbBFJU+N3+kEDKaXMAZJ/SjhHXXxaO3Ctdbid0zOPUP LKW8c/fZU1hAvsygp9sHzcpbPk4HvGy/K07IPvtMB6MicUS8QPxL2Cv7POc9Ar0S JODT6lBOF8sh5Vfj8WRSMa4/2ndXwbISKXIOv1q05egQbL6UEKSvaNyhlmGEI1fb M6EzizrxB86O/vl4um4IYSMIIzmK5ks5MvWk/xAzDy0qj1IXw3b8hSJ7Q1+urvIF xRKZbgLDBWRFINR8Qq8haNxnl4p6r5CBFXpiSEOK+rbvutK6YItse/s/zbwMDLpf Zbj9kXzoFQzfvYYqH+f3+Z99mBzszKuUaCcPPUgsAE6RTQ+9M+0flxjtyr/D13Kg k5Kw6XQwctjbOdHzEIn23qkykjL5zSdcdqN+9jK+QJFmYorXpQZiDXNw/9WNMM+t Yamw6YtYC4maWjMxT1LTWC6u1k7WzpEzxvLNi7uBWAS+9YE6nzYqOcroEkm/Pk0c Uvgu6amMQl7CY3mrgP4RagapNUbNPXo4+JyWODWlUVxTdVd07wN6DKCcCxipa7Bn 6tFbjVIcaFZLz+/DN4ZlzX3oTjeu//9QjMwJzwp71NEynacqrWk= =TTNz -----END PGP SIGNATURE----- --fALL9UhP4IJsq69l--