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[34.76.240.140]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fc8aa0078sm17977354f8f.59.2025.09.29.05.24.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Sep 2025 05:24:31 -0700 (PDT) Date: Mon, 29 Sep 2025 12:24:28 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: Daniel Mentz , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Will Deacon , Pranjal Shrivastava , Liviu Dudau , Rob Clark Subject: Re: [PATCH 2/2] drivers/arm-smmu-v3: Implement .iotlb_sync_map callback Message-ID: References: <20250927223953.936562-1-danielmentz@google.com> <20250927223953.936562-2-danielmentz@google.com> <20250929115803.GF2617119@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250929115803.GF2617119@nvidia.com> On Mon, Sep 29, 2025 at 08:58:03AM -0300, Jason Gunthorpe wrote: > On Sat, Sep 27, 2025 at 10:39:53PM +0000, Daniel Mentz wrote: > > @@ -3700,6 +3713,7 @@ static const struct iommu_ops arm_smmu_ops = { > > .map_pages = arm_smmu_map_pages, > > .unmap_pages = arm_smmu_unmap_pages, > > .flush_iotlb_all = arm_smmu_flush_iotlb_all, > > + .iotlb_sync_map = arm_smmu_iotlb_sync_map, > > Shouldn't this avoid defining the op on coherent systems? Does that mean we need to have 2 iommu_ops, one for coherent/non-coherent SMMUs, as both can be mixed in the same system. The current implementation would skip the page table call on coherent SMMUs, As in the first patch it only sets the pointer for them: .iotlb_sync_map = cfg->coherent_walk ? NULL : arm_lpae_iotlb_sync_map. Thanks, Mostafa > > Jason