public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Niklas Cassel <cassel@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: "Manivannan Sadhasivam" <mani@kernel.org>,
	"Bjorn Helgaas" <helgaas@kernel.org>,
	manivannan.sadhasivam@oss.qualcomm.com,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,
	"David E. Box" <david.e.box@linux.intel.com>,
	"Kai-Heng Feng" <kai.heng.feng@canonical.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Chia-Lin Kao" <acelan.kao@canonical.com>,
	"Dragan Simic" <dsimic@manjaro.org>,
	linux-rockchip@lists.infradead.org, regressions@lists.linux.dev,
	"FUKAUMI Naoki" <naoki@radxa.com>
Subject: Re: [PATCH v2 1/2] PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for devicetree platforms
Date: Wed, 15 Oct 2025 17:23:21 +0200	[thread overview]
Message-ID: <aO-8aeJdvApesEqi@ryzen> (raw)
In-Reply-To: <7df0bf91-8ab1-4e76-83fa-841a4059c634@rock-chips.com>

On Wed, Oct 15, 2025 at 09:00:41PM +0800, Shawn Lin wrote:
> For now, this is a acceptable option if default ASPM policy enable L1ss
> w/o checking if the HW could supports it... But how about adding
> supports-clkreq stuff to upstream host driver directly? That would help
> folks enable L1ss if the HW is ready and they just need adding property
> to the DT.

I like your idea, if you have time, please send a patch.

However, adding (working) support for L1 substates (via 'supports-clkreq')
is new code, and should thus be queued for next release instead of v6.18.

For now, pcie-dw-rockchip.c is broken for a lot of PCIe devices, so the
fix should be minimal and target v6.18, i.e. something like:
https://lore.kernel.org/linux-pci/20251015123142.392274-2-cassel@kernel.org/

Support for L1 substates via 'supports-clkreq' can be added on top of that
patch (while targeting v6.19).


Kind regards,
Niklas

  reply	other threads:[~2025-10-15 15:23 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-22 16:16 [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Manivannan Sadhasivam via B4 Relay
2025-09-22 16:16 ` [PATCH v2 1/2] PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for " Manivannan Sadhasivam via B4 Relay
2025-10-14 16:30   ` FUKAUMI Naoki
2025-10-14 18:49     ` Bjorn Helgaas
2025-10-14 23:33       ` Dragan Simic
2025-10-15  6:22         ` Manivannan Sadhasivam
2025-10-15 11:23           ` Diederik de Haas
2025-10-23 18:57           ` Dragan Simic
2025-10-15  6:26       ` Manivannan Sadhasivam
2025-10-15  7:13         ` FUKAUMI Naoki
2025-10-15  7:50           ` Manivannan Sadhasivam
2025-10-15  9:11             ` Shawn Lin
2025-10-15  9:43               ` Manivannan Sadhasivam
2025-10-15  9:46               ` Niklas Cassel
2025-10-15 10:33                 ` Manivannan Sadhasivam
2025-10-15 12:17                   ` Niklas Cassel
2025-10-15 13:00                     ` Shawn Lin
2025-10-15 15:23                       ` Niklas Cassel [this message]
2025-10-15 23:30                       ` Bjorn Helgaas
2025-10-16  6:46                         ` Hongxing Zhu
2025-10-17  3:36                         ` Manivannan Sadhasivam
2025-10-17  9:47                           ` Shawn Lin
2025-10-17 10:04                             ` Manivannan Sadhasivam
2025-10-17 12:19                               ` Shawn Lin
2025-10-17 12:54                                 ` Manivannan Sadhasivam
2025-10-17 13:45                                   ` Bjorn Helgaas
2025-10-31  6:21                                     ` Manivannan Sadhasivam
2025-10-15 12:26       ` Diederik de Haas
2025-10-15 22:50         ` Bjorn Helgaas
2025-10-16 17:38           ` Diederik de Haas
2025-10-30 22:14       ` Bjorn Helgaas
2025-10-30 22:16         ` Bjorn Helgaas
2026-01-22 12:12   ` Jon Hunter
2026-01-22 13:17     ` Manivannan Sadhasivam
2026-01-22 13:43       ` Jon Hunter
2026-01-22 14:39         ` Manivannan Sadhasivam
2026-01-22 15:29     ` Bjorn Helgaas
2026-01-22 17:01       ` Manivannan Sadhasivam
2026-01-22 19:14         ` Jon Hunter
2026-01-23 10:55           ` Jon Hunter
2026-01-23 13:56             ` Manivannan Sadhasivam
2026-01-23 14:39               ` Jon Hunter
2026-02-16 14:03               ` Jon Hunter
2026-02-16 14:18                 ` Manivannan Sadhasivam
2026-02-16 14:35                   ` Jon Hunter
2026-02-19 17:42                     ` Jon Hunter
2026-02-26 10:34                       ` Jon Hunter
2026-02-26 11:08                         ` Manivannan Sadhasivam
2026-02-26 16:55                           ` Jon Hunter
2026-03-03 16:27                             ` Manivannan Sadhasivam
2026-02-26 11:16                       ` Manivannan Sadhasivam
2026-02-26 16:52                         ` Jon Hunter
2026-03-03 16:17                           ` Manivannan Sadhasivam
2026-03-06 16:03                             ` Jon Hunter
2026-03-09  8:00                               ` Manivannan Sadhasivam
2026-02-16 17:19         ` Claudiu Beznea
2026-02-18 13:56           ` Manivannan Sadhasivam
2025-09-22 16:16 ` [PATCH v2 2/2] PCI: qcom: Remove the custom ASPM enablement code Manivannan Sadhasivam via B4 Relay
2025-09-23 23:14 ` [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Bjorn Helgaas
2025-11-08 16:18 ` Dmitry Baryshkov
2025-11-11  6:51   ` Val Packett
2025-11-11  7:19     ` Manivannan Sadhasivam
2025-11-11  7:40       ` Val Packett
2025-11-11 10:06         ` Manivannan Sadhasivam
2025-11-11 17:29           ` Val Packett
2025-11-13  4:30             ` Val Packett
2025-11-11 23:33     ` Bjorn Helgaas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aO-8aeJdvApesEqi@ryzen \
    --to=cassel@kernel.org \
    --cc=acelan.kao@canonical.com \
    --cc=bhelgaas@google.com \
    --cc=david.e.box@linux.intel.com \
    --cc=dsimic@manjaro.org \
    --cc=helgaas@kernel.org \
    --cc=hkallweit1@gmail.com \
    --cc=kai.heng.feng@canonical.com \
    --cc=kwilczynski@kernel.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-rockchip@lists.infradead.org \
    --cc=lpieralisi@kernel.org \
    --cc=mani@kernel.org \
    --cc=manivannan.sadhasivam@oss.qualcomm.com \
    --cc=naoki@radxa.com \
    --cc=rafael@kernel.org \
    --cc=regressions@lists.linux.dev \
    --cc=robh@kernel.org \
    --cc=shawn.lin@rock-chips.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox