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X-OriginatorOrg: opensource.cirrus.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2025 12:11:26.4517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 600f3647-2c0e-4065-447d-08de059aa3ef X-MS-Exchange-CrossTenant-Id: bec09025-e5bc-40d1-a355-8e955c307de8 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bec09025-e5bc-40d1-a355-8e955c307de8;Ip=[84.19.233.75];Helo=[edirelay1.ad.cirrus.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR19MB8034 X-Proofpoint-ORIG-GUID: wL0J7trw9ca-R4AfBZwvjIBFQnYrNlQ7 X-Proofpoint-GUID: wL0J7trw9ca-R4AfBZwvjIBFQnYrNlQ7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA3MDA5NyBTYWx0ZWRfX3messJ2xMFI4 xcb6RJG4e7trTdlrS9Aei3oUQCmtcgUY8BPzNJiFpl4MfO93obycqN3rO45kRUyLMuEwCrAE2ki mEF44uHJm7wMA0qfzrUZXl5lNh/x91cculZUgrIcln18+LjEZxeOliQU90t22AxkXAYK4O85+Lb FxOMdD02oU2Yrpe/eZxXFulohdysvZ+MLbsIvuZ5GSSnIDFzCTIlWYOZbbBtJU9aONss4hIggKb I+Ob0tqAK8J5VvpfWfqsnnuQQpiN1xyC1Xdxqa8A4RsKqKYf4oOieNz1wi1kIKBN9e4b/TKWSv7 5aJhsBAH1X71ouHZ2orV5Z2VFFUZ4lFreiKNhpelv1FqCtagcsaNYCXJUuoImg97kY/jds+JyU4 /U6P0bqfiD1vKPM7/HSmddGo2WjZwg== X-Authority-Analysis: v=2.4 cv=ePceTXp1 c=1 sm=1 tr=0 ts=68e50372 cx=c_pps a=5g1Slaqcz6OQozqf5DRlqw==:117 a=h1hSm8JtM9GN1ddwPAif2w==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=z/mQ4Ysz8XfWz/Q5cLBRGdckG28=:19 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s63m1ICgrNkA:10 a=RWc_ulEos4gA:10 a=w1d2syhTAAAA:8 a=AxrGpO7ZFrR7dZ43Va4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-Spam-Reason: safe On Tue, Oct 07, 2025 at 07:22:10PM +0800, Sune Brian wrote: > Charles Keepax 於 2025年10月7日 週二 下午6:30寫道： > > On Fri, Oct 03, 2025 at 05:13:04PM +0800, Brian Sune wrote: > > > The original WM8978 codec driver did not set the BCLK (bit clock) > > > divider, which can cause audio clocks to be incorrect or unstable > > > depending on the sample rate and word length. > > > > This isn't totally accurate, the driver expects it will be set > > through the set_clkdiv callback. Which one could probably argue > > is a bit of a more legacy approach, but probably worth calling > > that out here. > > According to actual hardware tests and the WM8978 driver study. > There are no bclk register setup in the entire driver. So I am not sure > How could this even set through the callback? The IC itself requires > 2-wires register load and this can't be done via software level. /* * Configure WM8978 clock dividers. */ static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) { struct snd_soc_component *component = codec_dai->component; struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component); int ret = 0; switch (div_id) { case WM8978_OPCLKRATE: ... case WM8978_BCLKDIV: if (div & ~0x1c) return -EINVAL; snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, div); <<---- HERE break; default: return -EINVAL; } dev_dbg(component->dev, "%s: ID %d, value %u\n", __func__, div_id, div); return ret; } Its not missing its right there. That said your way is probably slightly more standard these days, but we should take care of the interaction between the two. Thanks, Charles